ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 95

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.4
7728G–AVR–06/10
Phase Correct PWM Mode
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the
interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM0A1:0 to three (See
actual OC0A value will only be visible on the port pin if the data direction for the port pin is set
as output. The PWM waveform is generated by setting (or clearing) the OC0A Register at the
compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at
the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will
result in a constantly high or low output (depending on the polarity of the output set by the
COM0A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The wave-
form generated will have a maximum frequency of f
This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
Output Compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope opera-
tion. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the com-
pare match between TCNT0 and OCR0A while upcounting, and set on the compare match
while downcounting. In inverting Output Compare mode, the operation is inverted. The
dual-slope operation has lower maximum operation frequency than single slope operation.
However, due to the symmetric feature of the dual-slope PWM modes, these modes are pre-
ferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the coun-
ter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for
one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on
ure
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent compare matches between
OCR0A and TCNT0.
10-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the
f
OCnxPWM
=
oc
-------------------- -
N
f
0
clk_I/O
A
256
= f
ATtiny87/ATtiny167
clk_I/O
Table 10-2 on page
/2 when OCR0A is set to zero.
101). The
Fig-
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