ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 65

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3.5
8.3.6
7728G–AVR–06/10
Pin Change Interrupt Flag Register – PCIFR
Pin Change Mask Register 1 – PCMSK1
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the ATtiny87/167, and will always read as zero.
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Initial Value
Initial Value
Read/Write
Read/Write
Bit
Bit
PCINT15
R/W
R
7
0
7
–
0
PCINT14
R/W
R
6
–
0
6
0
PCINT13
R/W
R
5
–
0
5
0
PCINT12
R/W
R
4
–
0
4
0
PCINT11
R/W
R
3
–
0
3
0
ATtiny87/ATtiny167
PCINT10
R/W
R
2
–
0
2
0
PCINT9
PCIF1
R/W
R/W
1
0
1
0
PCINT8
PCIF0
R/W
R/W
0
0
0
0
PCMSK1
PCIFR
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