ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 194

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4
194
Starting a Conversion
ATtiny87/ATtiny167
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is
in progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering
is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA register. The trig-
ger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB register (see
description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on
the selected trigger signal, the ADC prescaler is reset and a conversion is started. This pro-
vides a method of starting conversions at fixed intervals. If the trigger signal still is set when
the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt
Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in
SREG register is cleared. A conversion can thus be triggered without causing an interrupt.
However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next
interrupt event.
Figure 17-2. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as
soon as the ongoing conversion has finished. The ADC then operates in Free Running mode,
constantly sampling and updating the ADC Data Register. The first conversion must be started
by writing a logical one to the ADSC bit in ADCSRA register. In this mode the ADC will perform
successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or
not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA
register to one. ADSC can also be used to determine if a conversion is in progress. The ADSC
bit will be read as one during a conversion, independently of how the conversion was started.
SOURCE 1
SOURCE n
. . .
. . .
. . .
. . .
ADSC
ADIF
ADTS[2:0]
Detector
Edge
ADATE
Start
ADC Prescaler
Conversion
CLK
Logic
CLK
IO
ADC
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