ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 122

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.8.1
12.8.2
12.9
122
Modes of Operation
ATtiny87/ATtiny167
Compare Output Function
Compare Output Mode and Waveform Generation
Figure 12-6. Compare Match Output Logic
The general I/O port function is overridden by the Output Compare (OC1A/B) from the Wave-
form Generator if either of the COM1A/B1:0 bits are set and if OCnxi respective bit is set in
TCCR1D register. However, the OC1A/Bi pin direction (input or output) is still controlled by the
Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1A/Bi
pin (DDR_OC1A/Bi) must be set as output before the OC1A/B value is visible on the pin. The
port override function is generally independent of the Waveform Generation mode, but there
are some exceptions. Refer to
The design of the Output Compare pin logic allows initialization of the OC1A/B state before the
output is enabled. Note that some COM1A/B1:0 bit settings are reserved for certain modes of
operation.
The COM1A/B1:0 bits have no effect on the Input Capture unit.
The Waveform Generator uses the COM1A/B1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM1A/B1:0 = 0 tells the Waveform Generator that no
action on the OC1A/B Register is to be performed on the next compare match. For compare
output actions in the non-PWM modes refer to
refer to
refer to
A change of the COM1A/B1:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect by
using the FOC1A/B strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare
Output mode (COM1A/B1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM1A/B1:0 bits control
whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
For non-PWM modes the COM1A/B1:0 bits control whether the output should be set, cleared
Table 12-2 on page
Table 12-3 on page
See “16-bit Timer/Counter Register Description” on page 132.
COMnx1
COMnx0
FOCnx
clk
I/O
Waveform
Generator
133, and for phase correct and phase and frequency correct PWM
133.
Table
OCnxi
12-1,
D
D
PORT
D
DDR
Table 12-2
OCnx
Q
Q
Q
Table 12-1 on page
and
1
0
Table 12-3
132. For fast PWM mode
for details.
OCnxi
Pin
7728G–AVR–06/10