ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 272

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26. Instruction Set Summary
272
Mnemonics
RCALL
RJMP
ICALL
CPSE
SBRC
SBRS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRGE
BRHS
BRHC
BRTC
BRVS
BRVC
ADIW
SBIW
CALL
BRMI
BRPL
BRTS
SUBI
SBCI
ANDI
COM
SBIC
BRLT
BRIE
BRID
ADD
ADC
AND
EOR
NEG
CBR
DEC
IJMP
RETI
CPC
SBIS
SUB
SBC
SBR
TST
CLR
SER
JMP
RET
ORI
INC
LSL
OR
CPI
SBI
CBI
CP
ATtiny87/ATtiny167
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rdl,K
Rd, K
Rd, K
Rd, K
Rd, K
Rd,Rr
Rd,Rr
Rd,Rr
Rdl,K
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
P,b
P,b
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Subtract with Carry Constant from Reg.
ARITHMETIC AND LOGIC INSTRUCTIONS
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Branch if Overflow Flag is Cleared
Subtract with Carry two Registers
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Cleared
Skip if Bit in I/O Register Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Branch if Overflow Flag is Set
Add with Carry two Registers
Skip if Bit in Register Cleared
Branch if Status Flag Cleared
Branch if Half Carry Flag Set
Branch if Interrupt Disabled
Skip if Bit in Register is Set
Branch if Interrupt Enabled
Branch if Same or Higher
Branch if Status Flag Set
Branch if T Flag Cleared
Relative Subroutine Call
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Clear Bit in I/O Register
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Direct Subroutine Call
Test for Zero or Minus
BIT AND BIT-TEST INSTRUCTIONS
Set Bit in I/O Register
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
Indirect Jump to (Z)
Branch if Not Equal
One’s Complement
Two’s Complement
Branch if Carry Set
Description
Add two Registers
Indirect Call to (Z)
Subroutine Return
Logical Shift Left
Interrupt Return
Branch if Lower
Branch if Minus
Branch if Equal
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
BRANCH INSTRUCTIONS
if (SREG(s) = 1) then PC PC+k + 1
if (SREG(s) = 0) then PC PC+k + 1
if (N
if (N
if (T = 1) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (H = 1) then PC
if (H = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (T = 0) then PC
if ( I = 1) then PC
if ( I = 0) then PC
if (Rd = Rr) PC
if (Rr(b)=0) PC
if (Rr(b)=1) PC
if (P(b)=0) PC
if (P(b)=1) PC
Rd(n+1)
Rdh:Rdl
Rdh:Rdl
Rd
V= 0) then PC
V= 1) then PC
Rd
PC
Rd
PC
Operation
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd
PC
PC
Rd
Rd
Rd
Rd
Rd
Rd
Rd
I/O(P,b)
I/O(P,b)
Rd
Rd Rr C
Rd
PC
PC
Rd Rr
PC
PC
Rd + Rr + C
Rd K
Rd - Rr - C
PC + k + 1
Rd(n), Rd(0)
PC + k + 1
Rd - K - C
0xFF Rd
0x00 Rd
Rd
Rd
Rd
Rd + Rr
Rd - Rr
Rd
Rd v Rr
Rdh:Rdl + K
Rd
STACK
STACK
Rd - K
Rdh:Rdl - K
Rd v K
Rd v K
Rd + 1
Rd 1
0xFF
(0xFF - K)
Z
Z
k
k
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
Rd
Rr
PC + k + 1
1
0
Rr
Rd
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
K
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
0
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Flags
Z,C,N,V
Z,C,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
I
7728G–AVR–06/10
#Clock
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
4
4
4
1
1
1
2
2
1