ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 158

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.4
158
ATtiny87/ATtiny167
USICR – USI Control Register
• Bits 3:0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read
or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock
edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC
strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock
operation a special feature is added that allows the clock to be generated by writing to the
USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an
external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately
be executed. Refer to the USISIF bit description on page 157 for further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt
when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. Refer to the USIOIF bit description on page 157 for further details.
• Bit 5:4 – USIWM1:0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and USI Data Register can therefore be clocked
externally, and data input sampled, even when outputs are disabled. The relations between
USIWM1:0 and the USI operation is summarized in
Bit
Read/Write
Initial Value
USISIE
R/W
7
0
USIOIE
R/W
6
0
USIWM1
R/W
5
0
USIWM0
R/W
4
0
Table
USICS1
R/W
3
0
14-1.
USICS0
R/W
2
0
USICLK
W
1
0
USITC
7728G–AVR–06/10
W
0
0
USICR