ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 151

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2
7728G–AVR–06/10
SPI Master Operation Example
The clock is generated by the Master device software by toggling the USCK pin via the PORT
Register or by writing a one to the USITC bit in USICR.
Figure 14-3. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in
reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0),
DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at nega-
tive edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e.,
samples data at negative and changes the output at positive edges. The USI clock modes cor-
responds to the SPI data mode 0 and 1.
Referring to the timing diagram
The following code demonstrates how to use the USI module as a SPI Master:
CYCLE
1. The Slave device and Master device sets up its data output and, depending on the
2. The Master generates a clock pulse by software toggling the USCK line twice (C and
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate
USCK
USCK
DO
SPITransfer:
SPITransfer_loop:
DI
protocol used, enables its output driver (mark A and B). The output is set up by writ-
ing the data to be transmitted to the USI Data Register. Enabling of the output is done
by setting the corresponding bit in the port Data Direction Register. Note that point A
and B does not have any specific order, but both must be at least one half USCK
cycle before point C where the data is sampled. This must be done to ensure that the
data setup requirement is satisfied. The 4-bit counter is reset to zero.
D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI
on the first edge (C), and the data output is changed on the opposite edge (D). The
4-bit counter will count both edges.
that the transfer is completed. The data bytes transferred must now be processed
before a new transfer can be initiated. The overflow interrupt will wake up the proces-
sor if it is set to Idle mode. Depending of the protocol used the slave device can now
set its output to high impedance.
( Reference )
sts
ldi
sts
ldi
A
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
B
MSB
MSB
C
1
D
2
6
6
(Figure
3
5
5
14-3), a bus transfer involves the following steps:
Figure 14-3
4
4
4
5
At the top of the figure is a USCK cycle
3
3
ATtiny87/ATtiny167
6
2
2
7
1
1
LSB
LSB
8
E
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