ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 63

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.3
8.3.1
8.3.2
7728G–AVR–06/10
External Interrupts Register Description
External Interrupt Control Register A – EICRA
External Interrupt Mask Register – EIMSK
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the ATtiny87/167, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 8-1.
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the ATtiny87/167, and will always read as zero.
Read/Write
Initial Value
Read/Write
Initial Value
ISCn1
0
0
1
1
Bit
Bit
Interrupt Sense Control
ISCn0
R
7
–
0
R
7
–
0
0
1
0
1
Table
Table
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge of INTn generates an interrupt request.
The rising edge of INTn generates an interrupt request.
R
6
–
0
R
6
–
0
8-1. The value on the INT1 pin is sampled before detecting
8-1. The value on the INT0 pin is sampled before detecting
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
ISC11
R/W
3
0
R
3
–
0
ATtiny87/ATtiny167
ISC10
R/W
2
0
R
2
–
0
ISC01
R/W
INT1
R/W
1
0
1
0
ISC00
R/W
INT0
R/W
0
0
0
0
EICRA
EIMSK
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