ATTINY167-15XD Atmel, ATTINY167-15XD Datasheet - Page 92

• Manufacturer Part Number: ATTINY167-15XD
• Description: MCU AVR 16K FLASH 15MHZ 20-TSSOP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY167-15XD

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 20-TSSOP
• Processor Series: ATTINY1x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.6.1
10.6.2
10.7
92
Modes of Operation
ATtiny87/ATtiny167
Compare Output Function
Compare Output Mode and Waveform Generation
Figure 10-4. Compare Match Output Logic
The general I/O port function is overridden by the Output Compare (OC0A) from the Wave-
form Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input
or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data
Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A
value is visible on the pin. The port override function is independent of the Waveform Genera-
tion mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action
on the OC0A Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 10-2 on page
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC0A strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare
Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For
non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or tog-
gled at a compare match
See ”8-bit Timer/Counter Register Description” on page 100.
COMnx1
COMnx0
FOCnx
clk
I/O
101, and for phase correct PWM refer to
(See ”Compare Match Output Unit” on page
Waveform
Generator
Table 10-1 on page
D
D
D
PORT
DDR
OCnx
Q
Q
Q
1
0
101. For fast PWM mode, refer to
Table 10-3 on page
91.).
OCnx
Pin
7728G–AVR–06/10
101.