ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 87

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.9.2.1
6.9.2.2
9111H–AUTO–01/11
Moving Interrupts Between Application and Boot Space, Atmel ATA6612 and ATA6613
MCU Control Register – MCUCR
When the BOOTRST Fuse is programmed, the Boot section size set to 2Kbytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical
and general program setup for the Reset and Interrupt Vector Addresses in ATA6613 is:
The MCU Control Register controls the placement of the Interrupt Vector table.
Note:
• Bit 1 – IVSEL: Interrupt Vector Select
Read/Write
Initial Value
Address Labels Code
;
.org 0x1C00
0x1C00
0x1C02
0x1C04
...
0x1C32
;
0x1C33
0x1C34
0x1C35
0x1C36
0x1C37
0x1C38
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the
Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning
of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash
Section is determined by the BOOTSZ Fuses. Refer to section
Read-While-Write Self-Programming, Atmel ATA6612 and ATA6613” on page 284
details. To avoid unintentional changes of Interrupt Vector tables, a special write proce-
dure must be followed to change the IVSEL bit:
Interrupts will automatically be disabled while this sequence is executed. Interrupts are
disabled in the cycle IVCE is set, and they remain disabled until after the instruction follow-
ing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles.
The I-bit in the Status Register is unaffected by the automatic disabling.
Bit
a. Write the Interrupt Vector Change Enable (IVCE) bit to one.
b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-
grammed, interrupts are disabled while executing from the Application section. If Interrupt
Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts
are disabled while executing from the Boot Loader section. Refer to section
port – Read-While-Write Self-Programming, Atmel ATA6612 and ATA6613” on page 284
details on Boot Lock bits.
RESET: ldi
R
7
–
0
jmp
jmp
jmp
...
jmp
out
ldi
out
sei
<instr>
R
6
–
0
RESET
EXT_INT0
EXT_INT1
...
SPM_RDY
r16,high(RAMEND); Main program start
SPH,r16
r16,low(RAMEND)
SPL,r16
xxx
R
5
–
0
PUD
R/W
4
0
Atmel ATA6612/ATA6613
Comments
; Reset handler
; IRQ0 Handler
; IRQ1 Handler
;
; Store Program Memory Ready Handler
; Set Stack Pointer to top of RAM
; Enable interrupts
R
3
–
0
R
2
–
0
IVSEL
R/W
“Boot Loader Support –
1
0
“Boot Loader Sup-
IVCE
R/W
0
0
MCUCR
for
for
87