ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 231

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.19.2.2
6.19.3
6.19.3.1
6.19.3.2
9111H–AUTO–01/11
Data Transfer and Frame Format
Electrical Interconnection
Transferring Bits
START and STOP Conditions
As depicted in
voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain
or open-collector. This implements a wired-AND function which is essential to the operation of
the interface. A low level on a TWI bus line is generated when one or more TWI devices output
a zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up
resistors to pull the line high. Note that all AVR
powered in order to allow any bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400pF and the 7-bit slave address space. A detailed specification of the electrical char-
acteristics of the TWI is given in
different sets of specifications are presented there, one relevant for bus speeds below
100kHz, and one valid for bus speeds up to 400kHz.
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The
level of the data line must be stable when the clock line is high. The only exception to this rule
is for generating start and stop conditions.
Figure 6-78. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated when
the Master issues a START condition on the bus, and it is terminated when the Master issues
a STOP condition. Between a START and a STOP condition, the bus is considered busy, and
no other master should try to seize control of the bus. A special case occurs when a new
START condition is issued between a START and STOP condition. This is referred to as a
REPEATED START condition, and is used when the Master wishes to initiate a new transfer
without relinquishing control of the bus. After a REPEATED START, the bus is considered
busy until the next STOP. This is identical to the START behavior, and therefore START is
used to describe both START and REPEATED START for the remainder of this datasheet,
unless otherwise noted. As depicted below, START and STOP conditions are signalled by
changing the level of the SDA line when the SCL line is high.
Figure 6-77 on page
SDA
SCL
“2-wire Serial Interface Characteristics” on page
Data Stable
230, both bus lines are connected to the positive supply
Data Change
Atmel ATA6612/ATA6613
®
devices connected to the TWI bus must be
Data Stable
324. Two
231