ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 262

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.20
6.20.1
262
Analog Comparator
Atmel ATA6612/ATA6613
ADC Control and Status Register B – ADCSRB
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trig-
ger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a
separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt trigger-
ing on comparator output rise, fall or toggle. A block diagram of the comparator and its
surrounding logic is shown in
The Power Reduction ADC bit, PRADC, in
must be disabled by writing a logical zero to be able to use the ADC input MUX.
Figure 6-99. Analog Comparator Block Diagram
Notes:
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
Initial Value
Read/Write
ADC MULTIPLEXER
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero),
the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is
written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a
detailed description of this bit (see
Bit
REFERENCE
ACME
ADEN
BANDGAP
OUTPUT
1. See
2. Refer to
AIN0
AIN1
(1)
Table 6-96 on page
ACBG
R
7
–
0
Table 6-38 on page 104
ACME
R/W
6
0
ACD
Figure
264.
R
5
–
0
VCC
6-99.
“Analog Comparator Multiplexed Input” on page
for Analog Comparator pin placement.
R
4
–
0
“Power Reduction Register - PRR” on page 66
(2)
ACIS1
R
3
–
0
INTERRUPT
SELECT
ACIS0
ADTS2
R/W
2
0
ACIC
ACIE
ACO
ADTS1
R/W
1
0
ADTS0
R/W
0
0
9111H–AUTO–01/11
TO T/C1 CAPTURE
TRIGGER MUX
ACI
ANALOG
COMPARATOR
IRQ
ADCSRB
264).