ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 44

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.5.2.1
6.5.3
6.5.3.1
44
Atmel ATA6612/ATA6613
EEPROM Data Memory
Data Memory Access Times
EEPROM Read/Write Access
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 6-10. On-chip Data SRAM Access Cycles
The Atmel
as a separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
The section
Programming in SPI or Parallel Programming mode.
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
tion, however, lets the user software detect when the next byte can be written. If the user code
contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-
tered power supplies, V
device for some period of time to run at a voltage lower than specified as minimum for the
clock frequency used. See
avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction
is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the
next instruction is executed.
®
Address
ATA6612/ATA6613 contains 512 bytes of data EEPROM memory. It is organized
“Memory Programming” on page 300
clk
Data
Data
WR
RD
CPU
CC
Compute Address
“Preventing EEPROM Corruption” on page 49
is likely to rise or fall slowly on power-up/down. This causes the
T1
Memory Access Instruction
Address valid
contains a detailed description on EEPROM
CPU
T2
Table 6-3 on page
cycles as described in
Next Instruction
T3
47. A self-timing func-
for details on how to
Figure
9111H–AUTO–01/11
6-10.