ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 294

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.23.7.8
6.23.7.9
294
Atmel ATA6612/ATA6613
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SELFPRGEN are set in
SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it is rec-
ommended to load the Z-pointer with 0x0001 (same as used for reading the lO
future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing
the Lock bits. When programming the Lock bits the entire Flash can be read during the
operation.
Note that an EEPROM write operation will block all software programming to Flash. Reading
the Fuses and Lock bits from software will also be prevented during the EEPROM write opera-
tion. It is recommended that the user checks the status bit (EEPE) in the EECR Register and
verifies that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the BLBSET and SELFPRGEN bits are
set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLB-
SET and SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no
LPM instruction is executed within three CPU cycles or no SPM instruction is executed within
four CPU cycles. When BLBSET and SELFPRGEN are cleared, LPM will work as described in
the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles
after the BLBSET and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low
byte (FLB) will be loaded in the destination register as shown below. Refer to
page 302
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the BLBSET and SELFPRGEN bits are set in
the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register
as shown below. Refer to
Fuse High byte.
Rd
Bit
Rd
Rd
Bit
Bit
for a detailed description and mapping of the Fuse Low byte.
FLB7
FHB7
7
7
–
7
FLB6
FHB6
Table 6-117 on page 302
6
6
–
6
BLB12
FLB5
FHB5
5
5
5
BLB11
FLB4
FHB4
4
4
4
BLB02
for detailed description and mapping of the
FLB3
FHB3
3
3
3
BLB01
FLB2
FHB2
2
2
2
FLB1
FHB1
LB2
1
1
1
FLB0
FHB0
Table 6-116 on
LB1
9111H–AUTO–01/11
0
0
0
ck
bits). For