ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 117

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.12.4.2
6.12.4.3
6.12.5
9111H–AUTO–01/11
Compare Match Output Unit
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-
ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock
is enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNT0 when using the Output Compare
Unit, independently of whether the Timer/Counter is running or not. If the value written to
TCNT0 equals the OCR0x value, the compare match will be missed, resulting in incorrect
waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the
counter is downcounting.
The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-
pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when
changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator
uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next compare
match. Also, the COM0x1:0 bits control the OC0x pin output source.
plified schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits,
and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control reg-
isters (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to
the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system
reset occur, the OC0x Register is reset to “0”.
Figure 6-30. Compare Match Output Unit, Schematic
COMnx1
COMnx0
FOCnx
clk
I/O
Waveform
Generator
D
D
D
PORT
DDR
OCnx
Atmel ATA6612/ATA6613
Q
Q
Q
1
0
Figure 6-30
OCnx
Pin
shows a sim-
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