ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 52

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.1.4
6.6.1.5
6.6.2
6.6.2.1
6.6.2.2
52
Atmel ATA6612/ATA6613
Clock Sources
Asynchronous Timer Clock – clk
ADC Clock – clk
Default Clock Source
Clock Startup Sequence
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O
clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC
conversion results.
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR
the appropriate modules.
Table 6-4.
Note:
The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures
that all users can make their desired clock source setting using any available programming
interface.
Any clock source needs a sufficient V
ing cycles before it can be considered stable.
To ensure sufficient V
the device reset is released by all other reset sources. The section
Reset” on page 68
timed from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTx
and CKSELx fuse bits. The selectable delays are shown in
quency of the Watchdog Oscillator is voltage dependent as shown in
page
ADC
Device Clocking Option
Low Power Crystal Oscillator
Full Swing Crystal Oscillator
Low Frequency Crystal Oscillator
Internal 128 kHz RC Oscillator
Calibrated Internal RC Oscillator
External Clock
Reserved
344.
1. For all fuses “1” means unprogrammed while “0” means programmed.
Device Clocking Options Select
ASY
describes the start conditions for the internal reset. The delay (t
CC
, the device issues an internal reset with a time-out delay (t
CC
to start oscillating and a minimum number of oscillat-
(1)
Table 6-5 on page
®
clock generator, and routed to
“Register Summary” on
“System Control and
1111 - 1000
0111 - 0110
0101 - 0100
CKSEL3..0
0011
0010
0000
0001
9111H–AUTO–01/11
53. The fre-
TOUT
TOUT
) after
) is