ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 130

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.12.8.6
6.12.8.7
130
Atmel ATA6612/ATA6613
Timer/Counter Interrupt Mask Register – TIMSK0
Timer/Counter 0 Interrupt Flag Register – TIFR0
• Bits 7..3 – Res: Reserved Bits
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
• Bits 7..3 – Res: Reserved Bits
• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
Initial Value
Initial Value
Read/Write
Read/Write
These bits are reserved bits in the Atmel
zero.
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is exe-
cuted if a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is
executed if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in
the Timer/Counter 0 Interrupt Flag Register – TIFR0.
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if
an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter
0 Interrupt Flag Register – TIFR0.
These bits are reserved bits in the Atmel ATA6612/ATA6613 and will always read as zero.
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the
data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by
writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare
B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Inter-
rupt is executed.
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the
data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by
writing a logic one to the flag.
Bit
Bit
R
R
7
–
0
7
–
0
R
6
–
0
R
6
–
0
R
5
–
0
R
5
–
0
R
4
–
0
R
4
–
0
®
ATA6612/ATA6613 and will always read as
R
3
–
0
R
3
–
0
OCIE0B
OCF0B
R/W
R/W
2
0
2
0
OCIE0A
OCF0A
R/W
R/W
1
0
1
0
TOIE0
TOV0
R/W
R/W
0
0
9111H–AUTO–01/11
0
0
TIMSK0
TIFR0