ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 68

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.7.8.6
6.7.8.7
6.8
6.8.1
68
System Control and Reset
Atmel ATA6612/ATA6613
Resetting the AVR
Port Pins
On-chip Debug System
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to
Disable Register 0 – DIDR0” on page 281
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode,
the main clock source is enabled and hence always consumes power. In the deeper sleep
modes, this will contribute significantly to the total current consumption.
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. For the Atmel
must be a JMP – Absolute Jump – instruction to the reset handling routine. For the Atmel
ATA6612, the instruction placed at the Reset Vector must be an RJMP – Relative Jump –
instruction to the reset handling routine. If the program never enables an interrupt source, the
Interrupt Vectors are not used, and regular program code can be placed at these locations.
This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors
are in the Boot section or vice versa (Atmel ATA6612/ATA6613 only). The circuit diagram in
Figure 6-15 on page 69
parameters of the reset circuitry.
The I/O ports of the AVR
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The
time-out period of the delay counter is defined by the user through the SUT and CKSEL
Fuses. The different selections for the delay period are presented in
52.
CC
I/O
/2 on an input pin can cause significant current even in active mode. Digital
“Digital Input Disable Register 1 – DIDR1” on page 264
) and the ADC clock (clk
®
shows the reset logic.
are immediately reset to their initial state when a reset source goes
“Digital Input Enable and Sleep Modes” on page 94
CC
/2, the input buffer will use excessive power.
®
ATA6613, the instruction placed at the Reset Vector
for details.
ADC
) are stopped, the input buffers of the device will
Table 6-20 on page 70
“Clock Sources” on page
defines the electrical
and
9111H–AUTO–01/11
“Digital Input
for details on