ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 60

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.6.9
6.6.10
6.6.11
60
Atmel ATA6612/ATA6613
Clock Output Buffer
Timer/Counter Oscillator
System Clock Prescaler
When applying an external clock, it is required to avoid sudden changes in the applied clock
frequency to ensure stable operation of the MCU. A variation in frequency of more than 2%
from one clock cycle to the next can lead to unpredictable behavior. If changes of more than
2% is required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. Refer to
page 60
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other
circuits on the system. The clock also will be output during reset, and the normal operation of
I/O pin will be overridden when the fuse is programmed. Any clock source, including the inter-
nal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock
Prescaler is used, it is the divided system clock that is output.
The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a
external clock source. The Timer/Counter Oscillator Pins (TOSC1 and TOSC2) are shared
with XTAL1 and XTAL2. This means that the Timer/Counter Oscillator can only be used when
an internal RC Oscillator is selected as system clock source. See
crystal connection.
Applying an external clock source to TOSC1 requires EXTCLK in the ASSR Register written to
logic one. See
description on selecting external clock as input instead of a 32kHz crystal.
The Atmel
divided by setting the
used to decrease the system clock frequency and the power consumption when the require-
ment for processing power is low. This can be used with all clock source options, and it will
affect the clock frequency of the CPU and all synchronous peripherals. clk
and clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher
than neither the clock frequency corresponding to the previous setting, nor the clock frequency
corresponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence,
it is not possible to determine the state of the prescaler - even if it were readable, and the
exact time it takes to switch from one clock division to the other cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before
the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
FLASH
for details.
®
ATA6612/ATA6613 has a system clock prescaler, and the system clock can be
are divided by a factor as shown in
“Asynchronous operation of the Timer/Counter” on page 180
“Clock Prescale Register – CLKPR” on page
Table 6-20 on page
“System Clock Prescaler” on
Figure 6-12 on page 53
70.
61. This feature can be
I/O
, clk
9111H–AUTO–01/11
ADC
for further
, clk
CPU
for
,