ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 123

• Manufacturer Part Number: ATA6613P-PLQW
• Description: MCU W/LIN TXRX REG WTCHDG 48-QFN
• Manufacturer: Atmel
• Series: AVR® ATA66 LIN-SBCr

Specifications of ATA6613P-PLQW

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.12.7
9111H–AUTO–01/11
Timer/Counter Timing Diagrams
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 6-34. Timer/Counter Timing Diagram, no Prescaling
Figure 6-35
Figure 6-35. Timer/Counter Timing Diagram, with Prescaler (f
• OCRnx changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
(clk
(clk
value is MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCnx value at MAX must correspond to
the result of an up-counting Compare Match.
misses the Compare Match and hence the OCnx change that would have happened on the
way up.
TCNTn
TCNTn
TOVn
TOVn
clk
clk
clk
I/O
I/O
clk
/1)
/8)
I/O
TN
TN
I/O
shows the same timing data, but with the prescaler enabled.
Figure 6-34
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 6-33 on page 122
MAX
MAX
Atmel ATA6612/ATA6613
Figure 6-33 on page
OCnx has a transition from high to low
BOTTOM
BOTTOM
clk_I/O
T0
122. When the OCR0A
/8)
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
123