ATA6613P-PLQW Atmel, ATA6613P-PLQW Datasheet - Page 236

MCU W/LIN TXRX REG WTCHDG 48-QFN

ATA6613P-PLQW

Manufacturer Part Number
ATA6613P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6613P-PLQW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA6613P-PLQW
Manufacturer:
ATMEL
Quantity:
5 000
Part Number:
ATA6613P-PLQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
6.19.5
6.19.5.1
236
Atmel ATA6612/ATA6613
Overview of the TWI Module
SCL and SDA Pins
The TWI module is comprised of several submodules, as shown in
drawn in a thick line are accessible through the AVR
Figure 6-85. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain
a slew-rate limiter in order to conform to the TWI specification. The input stages contain a
spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in
the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA
pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate
the need for external ones.
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Spike
Filter
Bus Interface Unit
Address/Data Shift
Spike Suppression
Register (TWDR)
Slew-rate
Control
SDA
Status Register
Ack
Spike
Filter
(TWSR)
®
data bus.
State Machine and
Control Unit
Status control
Bit Rate Generator
Control Register
Bit Rate Register
Prescaler
(TWCR)
Figure
(TWBR)
6-85. All registers
9111H–AUTO–01/11

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