CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 9

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16. System Resets
17. POR and LVD
18. SPI
15.3 Register Definitions...............................................................................................................122
15.4 Timing Diagrams...................................................................................................................130
16.1 Architectural Description.......................................................................................................135
16.2 Pin Behavior During Reset ...................................................................................................135
16.3 Register Definitions...............................................................................................................137
16.4 Timing Diagrams...................................................................................................................139
16.5 Power Modes........................................................................................................................141
17.1 Architectural Description.......................................................................................................143
17.2 Register Definitions...............................................................................................................144
18.1 Architectural Description.......................................................................................................145
15.3.1 I2C_XCFG Register .................................................................................................122
15.3.2 I2C_XSTAT Register................................................................................................123
15.3.3 I2C_ADDR Register.................................................................................................123
15.3.4 I2C_BP Register ......................................................................................................123
15.3.5 I2C_CP Register ......................................................................................................124
15.3.6 CPU_BP Register ....................................................................................................124
15.3.7 CPU_CP Register....................................................................................................124
15.3.8 I2C_BUF Register....................................................................................................125
15.3.9 I2C_CFG Register ..................................................................................................126
15.3.10 I2C_SCR Register ..................................................................................................128
15.3.11 I2C_DR Register .....................................................................................................129
15.4.1 Clock Generation .....................................................................................................130
15.4.2 Basic I/O Timing.......................................................................................................130
15.4.3 Status Timing ...........................................................................................................131
15.4.4 Slave Stall Timing ....................................................................................................132
15.4.5 Implementation ........................................................................................................132
15.4.6 Compatibility Mode Configuration ............................................................................133
16.2.1 GPIO Behavior on Power Up...................................................................................135
16.2.2 Powerup External Reset Behavior ...........................................................................136
16.2.3 GPIO Behavior on External Reset ...........................................................................136
16.3.1 CPU_SCR1 Register ...............................................................................................137
16.3.2 CPU_SCR0 Register ...............................................................................................138
16.4.1 Power On Reset ......................................................................................................139
16.4.2 External Reset .........................................................................................................139
16.4.3 Watchdog Timer Reset ............................................................................................139
16.4.4 Reset Details ...........................................................................................................141
17.2.1 VLT_CR Register .....................................................................................................144
17.2.2 VLT_CMP Register ..................................................................................................144
18.1.1 SPI Protocol Function ..............................................................................................145
18.1.2 SPI Master Function ................................................................................................146
18.1.3 SPI Slave Function ..................................................................................................146
18.1.4 Input Synchronization ..............................................................................................147
18.1.1.1 SPI Protocol Signal Definitions..................................................................146
18.1.2.1 Usability Exceptions ..................................................................................146
18.1.2.2 Block Interrupt ...........................................................................................146
18.1.3.1 Usability Exceptions ..................................................................................146
18.1.3.2 Block Interrupt ...........................................................................................147
Contents
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