CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 52

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.3.6
This register is used to enable the individual sources' ability
to create pending interrupts.
When an interrupt is masked off, the mask bit is '0'. The
interrupt still posts in the interrupt controller. Therefore,
clearing the mask bit only prevents a posted interrupt from
becoming a pending interrupt.
Bit 5: USB Wakeup. ’0’ is mask USB Wakeup interrupt. ‘1’
is unmask USB Wakeup interrupt.
Bit 4: Endpoint8. ’0’ is mask USB Endpoint8 interrupt. ‘1’ is
unmask USB Endpoint8 interrupt.
Bit 3: Endpoint7. ’0’ is mask USB Endpoint7 interrupt. ‘1’ is
unmask USB Endpoint7 interrupt.
5.3.7
The Interrupt Software Enable Register (INT_SW_EN) is
used to enable software interrupts.
Bit 0: ENSWINT. This bit is a special non-mask bit that
controls the behavior of the INT_CLR0 register. See the
INT_CLR0 register in this section for more information.
5.3.8
The Interrupt Vector Clear Register (INT_VC) returns the
next pending interrupt and clears all pending interrupts when
written.
Bits 7 to 0: Pending Interrupt[7:0]. When the register is
read, the least significant byte (LSB) of the highest priority
pending interrupt is returned. For example, if the GPIO and
I2C interrupts were pending and the INT_VC register was
read, the value 14h is read. However, if no interrupts were
pending, the value 00h is returned. This is the reset vector in
the interrupt table; however, reading 00h from the INT_VC
register is not considered an indication that a system reset is
Interrupt Controller
52
0,DEh
0,E1h
0,E2h
LEGEND
Clearable register or bits.
Address
Address
Address
INT_MSK2
INT_SW_EN
INT_MSK2 Register
INT_SW_EN Register
INT_VC Register
INT_VC
Name
Name
Name
Bit 7
Bit 7
Bit 7
Bit 6
Bit 6
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
USB Wakeup
Bit 5
Bit 5
Bit 5
Endpoint8
Pending Interrupt[7:0]
Bit 4
Bit 4
Bit 4
Bit 2: Endpoint6. ’0’ is mask USB Endpoint6 interrupt. ‘1’ is
unmask USB Endpoint6 interrupt.
Bit 1: Endpoint5. ’0’ is mask USB Endpoint5 interrupt. ‘1’ is
unmask USB Endpoint5 interrupt.
Bit 0: Endpoint4. ’0’ is mask USB Endpoint4 interrupt. ‘1’ is
unmask USB Endpoint4 interrupt.
For additional information, refer to the
on page
For additional information, refer to the
on page
pending. Rather, reading 00h from the INT_VC register sim-
ply indicates that there are no pending interrupts. The high-
est priority interrupt, indicated by the value returned by a
read of the INT_VC register, is removed from the list of
pending interrupts when the M8C services an interrupt.
Reading the INT_VC register has limited usefulness. If inter-
rupts are enabled, a read to the INT_VC register is not able
to determine that an interrupt was pending before the inter-
rupt was actually taken. However, while in an interrupt ser-
vice routine, a user may wish to read the INT_VC register to
see the next interrupt. When the INT_VC register is written
Endpoint7
248.
251.
Bit 3
Bit 3
Bit 3
Endpoint6
Bit 2
Bit 2
Bit 2
Endpoint5
Bit 1
Bit 1
Bit 1
INT_SW_EN register
INT_MSK2 register
ENSWINT
Endpoint4
Bit 0
Bit 0
Bit 0
Access
RC : 00
Access
Access
RW : 00
RW : 0
[+] Feedback