CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 148

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.2.2
The SPI Receive Data Register (SPI_RXR) is the SPI’s
receive data register. A write to this register clears the RX
Reg Full status bit in the Control register (SPI_CR).
18.2.2.1
There are two 8-bit Data registers and one 8-bit Control/Status register.
Receive registers in the context of SPIM operation.
Table 18-2. SPIM Data Register Descriptions
18.2.2.2
There are two 8-bit Data registers and one 8-bit Control/Status register.
Receive registers in the context of SPIS operation.
Table 18-3. SPIS Data Register Descriptions
SPI
148
0,2Ah
SPI_TXR
SPI_RXR
SPI_TXR
SPI_RXR
Address
Name
Name
SPI_RXR
SPI_RXR Register
TX Buffer
RX Buffer
TX Buffer
RX Buffer
SPI Master Data Register Definitions
SPI Slave Data Register Definitions
Name
Function
Function
Write only register.
If no transmission is in progress and this register is written to, the data from this register is loaded into the Shift register on
the following clock edge, and a transmission is initiated. If a transmission is currently in progress, this register serves as a
buffer for TX data.
This register must only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in the
Control register. When the data is transferred from this register to the Shift register, then TX Reg Empty status is set.
Read only register.
When a byte transmission/reception is complete, the data in the shifter is transferred into the RX Buffer register and RX Reg
Full status is set in the Control register.
A read from this register clears the RX Reg Full status bit in the Control register.
Write only register.
This register must only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in the
Control register. When the data is transferred from this register to the Shift register, then TX Reg Empty status is set.
Read only register.
When a byte transmission/reception is complete, the data in the shifter is transferred into the RX Buffer register and RX Reg
Full status is set in the Control register.
A read from this register clears the RX Reg Full status bit in the Control register.
Bit 7
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
Bit 4
Bits 7 to 0: Data[7:0]. These bits encompass the SPI
Receive register. They are discussed by function type in
Table 18-2
For additional information, refer to the
page
Data[7:0]
191.
Description
Description
Table 18-2
Table 18-3
Bit 3
and
Table
explains the meaning of the Transmit and
explains the meaning of the Transmit and
Bit 2
18-3.
Bit 1
SPI_RXR register on
Bit 0
Access
R : 00
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