CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 137

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3
The following registers are associated with the PSoC System Resets and are listed in address order. Each register descrip-
tion has an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of 0. For a
complete table of system reset registers, refer to the
16.3.1
The System Status and Control Register 1 (CPU_SCR1)
conveys the status and control of events related to internal
resets and watchdog reset.
Bit 7: IRESS. Internal Reset Status. This bit is a read only
bit that determines if the booting process occurred more
than once.
When this bit is set, it indicates that the SROM SWBootRe-
set code executed more than once. If this bit is not set, the
SWBootReset executed only once. In either case, the
SWBootReset code does not allow execution from code
stored in Flash until the M8C core is in a safe operating
mode with respect to supply voltage and Flash operation.
There is no need for concern when this bit is set. It is pro-
vided for systems that may be sensitive to boot time, so that
they can determine if the normal one-pass boot time was
exceeded.
For more information on the SWBootReest code see the
Supervisory ROM (SROM) chapter on page
Bit 4:3 SLIMO[1:0]. These bits set the IMO frequency
range. See the table ahead for more information. These
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
x,FEh
LEGEND
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
# Access is bit specific. Refer to the
Address
Register Definitions
CPU_SCR1
CPU_SCR1 Register
Name
IRESS
Bit 7
Register Reference chapter on page 187
Bit 6
89.
Bit 5
“Summary Table of the System Resource Registers” on page
Bit 4
for additional information.
SLIMO[1:0]
changes allow for optimization of speed and power. The
IMO trim value must also be changed when SLIMO is
changed (see
When not in external clocking mode, the IMO is the source
for SYSCLK; therefore, when the speed of the IMO changes
so does SYSCLK.
Bit 0: IRAMDIS. Initialize RAM Disable. This bit is a control
bit that is readable and writeable. The default value for this
bit is ‘0’, which indicates that the maximum amount of SRAM
must be initialized on watchdog reset to a value of 00h.
When the bit is ‘1’, the minimum amount of SRAM is initial-
ized after a watchdog reset.
For additional information, refer to the
on page
00
01
10
11
SLIMO
Bit 3
257.
Engaging Slow IMO on page
12
6
24
Reserved
Bit 2
CY8CTMG20x, CY8CTST200
Bit 1
IRAMDIS
CPU_SCR1 register
Bit 0
63).
System Resets
106.
Access
# : 0
137
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