CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 132

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.4.4
When a byte complete interrupt occurs, the PSoC device firmware must respond with a write to the
tinue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see
ing on page
I2C_SCR
and the next rising edge of SCL is always N-1 clocks.
15.4.5
The I2C block responds to transactions during sleep if and
only if:
To enable the wakeup through I2C, set the HW Addr EN bit
so that the I2C slave block wakes the system if and only if
the address matches.
sequence through I2C.
Note The last step in this flowchart where SCL is released in
general, represents the configuration where buffer mode is
enabled.
I2C Slave
132
a. The I2C slave block is enabled, i.e., bit 0 of the
b. If I2C_ON is set or the USB Enable bit of USB_CR0
c. PD signal from the sleep controller is high.
I2C_CFG Register
is set.
Register; otherwise, a stall occurs. After stalled, the I/O write releases the stall. The setup time between data output
131). As illustrated in
Slave Stall Timing
Implementation
(Synchronized)
I/O WRITE
SDA_OUT
SCL_OUT
Figure 15-12
SCL_IN
CLOCK
is set to 1'b1.
SCL
Figure
depicts the wakeup
15-11, firmware has until one clock after the falling edge of SCL_IN to write to the
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
No STALL
Figure 15-11. Slave Stall Timing
1 Clocks
Figure 15-12. I2C Wakeup Sequence
STALL
Send NACK
No
N-1 Clocks
Wakeup system by interrupt
ACK the address byte and
No
release the SCL line once
No
and pull the SCL low
IMO is operational
Device Address
I2C_SCR Register
I2C Sleep
Matched?
Enabled?
Detect
Start
Yes
Yes
Yes
Status Tim-
to con-
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