CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 208

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CMP_CR1
21.3.21 CMP_CR1
This register is used to configure the comparator output options.
For additional information, refer to the
Bit
7
6
5
4
3
2
1
(continued on next page)
208
Individual Register Names and Addresses:
CMP_CR1 : 0,7Bh
Access : POR
Bit Name
0,7Bh
CINT1
CPIN1
CRST1
CDS1
CINT0
CPIN0
CRST0
Name
Comparator Control Register 1
RW : 0
CINT1
7
RW : 0
CPIN1
6
Description
This bit selects comparator 1 for input to the analog interrupt. Note that if both CINT1 and CINT0 are
set high, a rising edge on either comparator output may cause an interrupt.
0
1
This bit selects the comparator 1 signal for possible connection to the GPIO pin. Connection to the
pin also depends on the configuration of the OUT_P1 register.
0
1
This bit selects the source for resetting the comparator 1 latch.
0
1
This bit selects the data output for the comparator 1 channel, for routing to the capacitive sense logic
and comparator 1 interrupt.
0
1
This bit selects comparator 0 for input to the analog interrupt. Note that if both CINT1 and CINT0 are
set high, a rising edge on either comparator output may cause an interrupt.
0
1
This bit selects the comparator 0 signal for possible connection to the GPIO pin. Connection to the
pin also depends on the configuration of the OUT_P1 register.
0
1
This bit selects the source for resetting the comparator 0 latch.
0
1
Register Definitions on page 103
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Comparator 1 does not connect to the analog interrupt.
Comparator 1 connects to the analog interrupt. A rising edge asserts that interrupt, if it is
enabled in the INT_MSK0 register.
Select comparator 1 LUT output.
Select comparator 1 Latch output.
Reset by writing a ‘0’ to the CMP_RDC register’s CMP1L bit.
Reset by rising edge of comparator 0 LUT output.
Select the comparator 1 LUT output.
Select the comparator 1 latch output.
Comparator 0 does not connect to the analog interrupt.
Comparator 0 connects to the analog interrupt. A rising edge asserts that interrupt, if it is
enabled in the INT_MSK0 register.
Select comparator 0 LUT output.
Select comparator 0 Latch output.
Reset by writing a ‘0’ to the CMP_RDC register’s CMP0L bit.
Reset by rising edge of comparator 1 LUT output.
CRST1
RW : 0
5
RW : 0
CDS1
4
in the Comparators chapter .
RW : 0
CINT0
3
RW : 0
CPIN0
2
CRST0
RW : 0
1
0,7Bh
RW : 0
CDS0
0
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