CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 39

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This chapter explains the PSoC device’s use of RAM Paging and its associated registers. For a complete table of the RAM
paging registers, refer to the
address order, refer to the
4.1
The M8C is an 8-bit CPU with an 8-bit memory address bus.
The memory address bus allows the M8C to access up to
256 bytes of SRAM, to increase the amount of available
SRAM and preserve the M8C assembly language. The
PSoC device has 1K and 2K bytes of SRAM with eight
pages of memory architecture.
To take full advantage of the paged memory architecture of
the PSoC device, you use several registers and manage
two CPU_F register bits. However, the Power On Reset
(POR) value for all of the paging registers and CPU_F bits is
zero. This places the PSoC device in a mode identical to
devices with only 256 bytes of SRAM. There is no need to
understand all of the Paging registers to take advantage of
the additional SRAM available in some devices. To use the
additional SRAM pages you modify the memory paging logic
reset state.
The memory paging architecture consists of five areas:
■
■
■
■
■
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
4. RAM Paging
FFh
00h
Stack Operations
Interrupts
MVI Instructions
Current Page Pointer
Indexed Memory Page Pointer
256 Bytes
Page 0
SRAM
Architectural Description
ISR
256 Bytes
Page 1
SRAM
Register Reference chapter on page
Summary Table of the Core Registers on page
256 Bytes
Page 2
SRAM
Figure 4-1. Data Memory Organization
256 Bytes
Page 3
SRAM
187.
The first three of these areas do not depend upon the
CPU_F register's PgMode bits and are covered in the next
subsections after Basic Paging. The function of the last two
depend upon the CPU_F PgMode bits and are covered last.
4.1.1
To increase the amount of SRAM, the M8C accesses mem-
ory page bits. The memory page bits are located in the
CUR_PP register and allow for selection of one of eight
SRAM pages. In addition to setting the page bits, Page
mode is enabled by setting the CPU_F[7] bit. If Page mode
is not enabled, the page bits are ignored and all non-stack
memory access is directed to Page 0.
After Page mode is enabled and the page bits are set, all
instructions that operate on memory access the SRAM page
indicated by the page bits. The exceptions to this are the
instructions that operate on the stack and the MVI instruc-
tions: PUSH, POP, LCALL, RETI, RET, CALL, and MVI. See
the description of
below for a more detailed discussion.
256 Bytes
Page 4
SRAM
24. For a quick reference of all PSoC registers in
Basic Paging
256 Bytes
Stack Operations
Page 5
SRAM
256 Bytes
Page 6
SRAM
and
MVI Instructions
256 Bytes
Page 7
SRAM
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