CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 172

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3.3
The USB I/O Control Register 0 (USBIO_CR0) is used for
manually transmitting on the USB D+ and D- pins, or read-
ing the differential receiver.
Bit 7: TEN. This is used to manually transmit on the D+ and
D- pins. Normally, this bit must be cleared to allow the inter-
nal SIE to drive the pins. The most common reason for man-
ually transmitting is to force a resume state on the bus. ‘0‘ is
manual transmission off (TSE0 and TD have no effect). ‘1‘ is
manual transmission enabled (TSE0 and TD determine the
state of the D+ and D- pins).
20.3.4
The USB I/O Control Register 1 (USBIO_CR1) is used to
manually read or write the D+ and D- pins, and to configure
internal pull up resistors on those pins.
Bit 7: IOMode. This bit allows the D+ and D- pins to be
configured for either USB mode or bit banged modes. If this
bit is set, the DMI and DPI bits are used to drive the D- and
D+ pins. ‘0‘ is USB mode. Drive mode has no effect. ‘1‘ is
drive mode, DMI and DPI determine state of the D+ and D-
pins.
Bit 6: Drive Mode. If the IOMode bit is set, this bit config-
ures the D- and D+ pins for either CMOS drive or open drain
drive. If IOMode is cleared, this bit has no effect. Note that in
open drain mode, 5 k Ω pull up resistors can be connected
internally with the PS2PUEN bit. ‘0‘ is D+ and D- are in open
drain mode. If the DPI or DMI bits are set high, the corre-
sponding D+ or D- pad is high impedance. ‘1‘ is D+ and D-
are in CMOS drive mode. D+ follows DPI and D- follows
DMI.
Full-Speed USB
172
0,34h
0,35h
Address
Address
USBIO_CR0
USBIO_CR1
USBIO_CR0 Register
USBIO_CR1 Register
Name
Name
IOMode
Bit 7
Bit 7
TEN
Drive Mode
TSE0
Bit 6
Bit 6
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Bit 5
TD
Bit 5
DPI
Bit 4
Bit 4
DMI
Bit 6: TSE0. Transmit Single-Ended Zero. SE0: both D+
and D- low. No effect if TEN=0. ‘0‘ is do not force SE0. ‘1‘ is
force SE0 on D+ and D-.
Bit 5: TD. Transmit a USB J or K state on the USB bus. No
effect if TEN=0 or TSE0=1. ‘0‘ forces USB K state (D+ is low,
D- is high). ‘1‘ forces USB J state (D+ is high, D- is low).
Bit 0: RD. This read only bit gives the state of the USB dif-
ferential receiver. ‘0‘ is D+ < D- or D+ = D- = 0. ‘1‘ is D+ > D-.
For additional information, refer to the
on page
Bit 5: DPI. This bit is used to drive the D+ pin if IOMode=1.
Refer to the Drive Mode bit for drive state of pad. ‘0‘ is drive
D+ pad low. ‘1‘ is drive D+ pad high (unless Drive Mode=0).
Bit 4: DMI. This bit is used to drive the D- pin if IOMode=1.
Refer to the Drive Mode bit for drive state of pad. ‘0‘ is drive
D- pad low. ‘1‘ is drive D- pad high (unless Drive Mode=0).
Bit 3: PS2PUEN. This bit controls the connection of the two
internal 5 k Ω pull up resistors to the D+ and D- pins. ‘0‘ is no
effect. ‘1‘ is apply 5k pull ups between Vdd and both D+ and
D- pads, independent of the IOMode and Drive Mode bits.
Bit 2: USBPUEN. This bit controls the connection of the
internal 1.5 k Ω pull up resistor on the D+ pin. ‘0‘ is no effect.
‘1‘ is apply internal USB pull up resistor to D+ pad.
Bit 1: DPO. This read only bit gives the state of the D+ pin.
Bit 0: DMO. This read only bit gives the state of the D- pin.
For additional information, refer to the
on page
PS2PUEN
Bit 3
Bit 3
196.
197.
USBPUEN
Bit 2
Bit 2
Bit 1
Bit 1
DPO
USBIO_CR0 register
USBIO_CR1 register
Bit 0
RD
DMO
Bit 0
Access
Access
# : 0
# : 03
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