CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 272

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IO_CFG1
21.4.14 IO_CFG1
This register is used to configure the Port 1 output regulator and set the interrupt mode for all GPIO.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
page 59
Bits
7
5:4
3
2
1
0
272
Individual Register Names and Addresses:
IO_CFG1 : 1,DCh
Access : POR
Bit Name
1,DCh
in the GPIO chapter.
StrongP
Range[1:0]
P1-LOW_THRS
SPICLK_ON_P10
REG_EN
IO INT
Name
Input/Output Configuration Register 1
StrongP
RW : 0
7
6
Description
Setting this bit increases the drive strength and edge ratio for high outputs.
Selects the high output level for Port 1 outputs.
00
01
10
11
This bit reduces the threshold voltage of the P1 port input buffers so that there are no compatibility
issues when Port 1 is communicating at regulated voltage levels.
0
1
When set to ‘1’, the SPI clock is mapped to Port 1 pin 0. Otherwise, it is mapped to Port 1 pin 3.
Controls the regulator on Port 1 outputs.
0
1
Sets the GPIO interrupt mode for all pins in the PSoC device. GPIO interrupts are also controlled at
each pin by the PRTxIE registers, and by the global GPIO bit in the INT_MSK0 register.
0
1
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
3.0 volts
3.0 volts
1.8 volts
2.5 volts
Standard threshold of VIH, VIL
Reduce threshold of VIH, VIL
Regulator disabled, so Port 1 strong outputs drive to Vdd.
Regulator enabled, so Port 1 strong outputs drive to approximately 3V (for Vdd > 3V).
GPIO interrupt configured for interrupt when pin is low.
GPIO interrupt configured for interrupt when pin state changes from last time port was read.
5
Range[1:0]
RW : 0
4
P1_LOW_
RW : 0
THRS
3
SPICLK_
ON_P10
RW : 0
2
1,DCh
REG_EN
RW : 0
Register Definitions on
1
RW : 0
IO INT
0
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