CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 89

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 11-10. Negative Charge Integration Block Diagram
The initialization phase for negative CI (charge integration)
is the same as for successive approximation
Following that, a two-phase sequence discharges the inte-
gration capacitor, as illustrated in
Figure
Figure 11-11. Negative Charge Integration First Phase:
Grounding the Sense Capacitor
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Vr
Comparator
Reference
IMO
Buffer
Vr
11-12.
Comparator
Reference
Buffer
REF_EN
Clock Select
TrueTouch
TrueTouch Logic
Mux
Mux
Open
16-Bit Counter
Mux
Mux
CSCLK and Pin Enables
CSCLK
Refs
Vref
Grounded
Closed
Closed
Figure 11-11
C
INTERNAL
s
(Figure
CSN
CS1
CS2
C
C
P0[1] or
EXTERNAL
EXTERNAL
P0[3]
CS1
CS2
CSN
11-7).
and
Figure 11-12. Negative Charge Integration Second Phase:
Integrating Charge onto Integration Capacitor
11.1.1.5
The sigma delta capacitive sensing operates by holding an
integration capacitor voltage near a target threshold, and
charging the voltage up or down based on the present state
of a comparator output. The sense capacitor is continuously
switched between ground and the integration capacitor,
which drives the integrated voltage down on each switching
cycle. When the integration voltage is below the reference
threshold, a current from the internal IDAC is used to charge
the capacitor above the threshold again. The TrueTouch
Sigma Delta (CSD) User Module in PSoC Designer uses
this method.
As the integration capacitor voltage moves back and forth
across the comparator threshold, the comparator "high" out-
puts are counted in an interval to give a measure of the
sense capacitor. The larger the sense capacitor, the more
time the comparator is low, and so the count is less.
To reduce noise, the sense capacitor is driven with a
pseudo-random sequence (PRS). An 8- or 12-bit sequence
can be selected, and the PRS is clocked from a prescaler
giving input rates of the main system clock or any divide-by-
two of this, down to SYSCLK/256. The counter accumulates
counts for a selected interval, typically the cycle length of
the PRS (511 or 1023 cycles of the PRS prescale clock).
When bit 0 (EN) and bit 3 (CSD_MODE) of the CS_CR0
register are set to ‘1’, the TrueTouch counters are enabled to
work in CSD mode. When both CMP0 (this input is double
synchronized) and the "START" signal from Programmable
Timer are ‘1’, the counters increment. When this comparator
output is low, the counters hold their count until the compar-
ator goes high again. In this case:
Vr
Com parator
Reference
Buffer
Sigma Delta
Open
Mux
Mux
Vref
Closed
Closed
TrueTouch Module
C
INTERNAL
CSN
CS1
CS2
C
EXTERNA
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