CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 147

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.1.3.2
The SPIS block has a selection of two interrupt sources:
Interrupt on TX Reg Empty (default) or interrupt on SPI
Complete (same selection as the SPIM). Mode bit 1 in the
Function register controls the selection.
If SPI Complete is selected as the block interrupt, the Con-
trol register must still be read in the interrupt routine so that
this status bit is cleared; otherwise, no subsequent inter-
rupts are generated.
18.2
The following registers are associated with the SPI and are listed in address order. The register descriptions have an associ-
ated register table showing the bit structure for that register. For a complete table of SPI registers, refer to the
of the System Resource Registers on page
Data Registers
18.2.1
The SPI Transmit Data Register (SPI_TXR) is the SPI’s
transmit data register.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,29h
Address
Register Definitions
SPI_TXR
SPI_TXR Register
Block Interrupt
Name
Bit 7
Bit 6
106.
Bit 5
Bit 4
18.1.4
All pin inputs are double synchronized to SYSCLK by
default. Synchronization can be bypassed by setting the
BYPS bit in the SPI_CFG register.
Bits 7 to 0: Data[7:0]. These bits encompass the SPI
Transmit register. They are discussed by function type in
Table 18-2
For additional information, refer to the
page
Data[7:0]
190.
Bit 3
and
Input Synchronization
Table
Bit 2
18-3.
Bit 1
SPI_TXR register on
Bit 0
Summary Table
Access
W : 00
147
SPI
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