CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 248

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INT_MSK2
21.3.57 INT_MSK2
This register enables the individual sources' ability to create pending interrupts.
When an interrupt is masked off, the mask bit is '0'. The interrupt continues to post in the interrupt controller. Clearing the
mask bit only prevents a posted interrupt from becoming a pending interrupt. In the table above, note that reserved bits are
grayed table cells and are not described in the bit description section below. Reserved bits must always be written with a
value of ‘0’. For additional information, refer to the
Bit
5
4
3
2
1
0
248
Individual Register Names and Addresses:
INT_MSK2 : 0,DEh
Access : POR
Bit Name
0,DEh
USB Wakeup
Endpoint8
Endpoint7
Endpoint6
Endpoint5
Endpoint4
Name
Interrupt Mask Register 2
7
6
Description
0
1
0
1
0
1
0
1
0
1
0
1
USB Wakeup
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Mask USB Wakeup interrupt.
Unmask USB Wakeup interrup.
Mask USB Endpoint8 interrupt.
Unmask USB Endpoint8 interrupt.
Mask USB Endpoint7 interrupt.
Unmask USB Endpoint7 interrupt.
Mask USB Endpoint6 interrupt.
Unmask USB Endpoint6 interrupt.
Mask USB Endpoint5 interrupt.
Unmask USB Endpoint5 interrupt.
Mask USB Endpoint4 interrupt.
Unmask USB Endpoint4 interrupt.
RW : 0
5
Register Definitions on page 48
0,DEh
Endpoint8
RW : 0
4
Endpoint7
RW : 0
3
in the Interrupt Controller chapter.
Endpoint6
RW : 0
2
Endpoint5
RW : 0
1
Endpoint4
RW : 0
0
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