CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 171

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.3
The following registers are related to Full-Speed USB in the PSoC device. For a complete table of the Full-Speed USB regis-
ters, refer to the Registers table
out in this document are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits
with a value of ‘0’.
20.3.1
The USB Start of Frame Registers (USB_SOF0 and
USB_SOF1) provide access to the 11-bit SOF frame num-
ber. Start of frame packets are sent from the host (for exam-
ple, the PC) every 1 ms. For more information, see the
Universal Serial Bus Specification, revision 2.0 .
20.3.2
The USB Control Register 0 (USB_CR0) is used to set the
PSoC’sUSB address and enable the USB system resource.
All bits in this register are reset to zero when a USB bus
reset interrupt occurs.
Note Set the IMO frequency to 24 MHz and enable the 48
MHz clock in the OSC_CR2 register before USB is enabled.
See IMO_TR and CPU_SCR1 registers for selecting IMO
frequency as 24 MHz.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
Address
0,31h
0,32h
Address
0,33h
USB_SOF0
USB_SOF1
USB_CR0
Register Definitions
USB_SOF0 Register
USB_CR0 Register
Name
Name
USB Enable
Bit 7
Bit 7
Summary Table of the System Resource Registers on page
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Frame Number[7:0]
Bit 4
Bits 7 to 0: Frame Number. The USB_SOF0 register has
the lower 8 bits [7:0] and the USB_SOF1 register has the
upper 3 bits [10:8] of the SOF frame number.
For additional information, refer to the
on page 193
Bit 7: USB Enable. This bit enables the PSoC device to
respond to USB traffic. ‘0’ is USB disabled. The device does
not respond to USB traffic. ‘1’ is USB enabled.
Bits 6 to 0: Device Address[6:0]. These bits specify the
USB device address to which the SIE responds. This
address must be set by firmware and is specified by the
USB host with a SET ADDRESS command during USB enu-
meration. This value must be programmed by firmware
when assigned during enumeration. It is not set automati-
cally by the hardware.
For additional information, refer to the
page
Device Address[6:0]
195.
Bit 3
Bit 3
and the
Bit 2
Bit 2
USB_SOF1 register on page
Frame Number[10:8]
106. Register bits that are grayed
Bit 1
Bit 1
USB_CR0 register on
USB_SOF0 register
Bit 0
Bit 0
Full-Speed USB
194.
Access
Access
RW : 00
R : 00
R : 0
171
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