CY8CTST200-48LTXIT Cypress Semiconductor Corp, CY8CTST200-48LTXIT Datasheet - Page 33

• Manufacturer Part Number: CY8CTST200-48LTXIT
• Description: IC MCU 32K FLASH 48-QFN
• Manufacturer: Cypress Semiconductor Corp
• Series: TrueTouch™r

Specifications of CY8CTST200-48LTXIT

• Applications: Touchscreen Controller
• Core Processor: M8C
• Program Memory Type: FLASH (32 kB)
• Controller Series: CY8CT
• Ram Size: 2K x 8
• Interface: I²C, SPI, UART/USART, USB
• Number Of I /o: 38
• Voltage - Supply: 1.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Processor Series: CY8CTxx2xx
• Core: M8C
• Data Bus Width: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

This chapter discusses the Supervisory ROM (SROM) functions. For a quick reference of all PSoC registers in address order,
refer to the
3.1
The SROM holds code that boots a PSoC device, calibrates
circuitry, and performs Flash operations. The functions pro-
vided by the SROM are called from code stored in the Flash
or by device programmers.
The SROM is used to boot the part and provide interface
functions to the Flash blocks.
functions.) The SROM functions are accessed by executing
the Supervisory System Call instruction (SSC), which has an
opcode of 00h. Before executing the SSC, the M8C's accu-
mulator needs to load with the wanted SROM function code
from
Attempting to access undefined functions (Reserved func-
tions) causes a HALT. The SROM functions execute code
with calls; therefore, the functions require stack space. With
the exception of Reset, all of the SROM functions have a
parameter block in SRAM that you must configure before
executing the SSC.
Table 3-2
meaning of each parameter, with regards to a specific
SROM function, is described later in this chapter. Because
the SSC instruction clears the CPU_F PgMode bits, all
parameter block variable addresses are in SRAM Page 0.
The CPU_F value is automatically restored at the end of the
SROM function.
The MVR_PP and the MVW_PP pointers are not disabled
by clearing the CPU_F PgMode bits. Therefore, the
POINTER parameter is interpreted as an address in the
page indicated by the MVI page pointers, when the supervi-
sory operation is called. This allows the data buffer used in
the supervisory operation to be located in any SRAM page.
(See the
regarding the MVR_PP and MVW_PP pointers.)
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
3. Supervisory ROM (SROM)
Table
RAM Paging chapter on page 39
lists all possible parameter block variables. The
3-1.
Register Reference chapter on page
Architectural Description
(Table 3-1
lists the SROM
for more details
187.
Table 3-1. List of SROM Functions
Note ProtectBlock and EraseAll (described on page 36) SROM functions are
not listed in the table above because they are dependent on external pro-
gramming.
Table 3-2. SROM Function Variables
Note CLOCK and DELAY are ignored and are reserved for future use.
Two important variables that are used for all functions are
KEY1 and KEY2. These variables are used to help discrimi-
nate between valid SSCs and inadvertent SSCs. KEY1 must
always have a value of 3Ah, while KEY2 must have the
same value as the stack pointer when the SROM function
begins execution. This is the SP (Stack Pointer) value when
the SSC opcode is executed, plus three. For all SROM func-
tions except SWBootReset, if either of the keys do not
match the expected values, the M8C halts. The SWBootRe-
set function does not check the key values. It only checks to
see if the accumulator's value is 0x00.
00h
01h
02h
03h
06h
07h
08h
09h
0Ah
0Fh
KEY1/RETURN CODE
KEY2
BLOCKID
POINTER
CLOCK
Reserved
DELAY
Reserved
Function Code
Variable Name
SWBootReset
ReadBlock
WriteBlock
EraseBlock
TableRead
CheckSum
Calibrate0
Calibrate1
WriteAndVerify
HWBootReset
Function Name
0
7
7
5
3
4
4
3
7
3
Stack Space
Required
0,F8h
0,F9h
0,FAh
0,FBh
0,FCh
0,FDh
0,FEh
0,FFh
SRAM Address
34
35
35
36
36
37
37
37
37
38
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