PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 81

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

5.3.5
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
more than the top half of Bank 15 (F40h to FFFh). A list
of these registers is given inTable 5-3, Table 5-4 and
Table 5-5.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
TABLE 5-3:
© 2009 Microchip Technology Inc.
Address
Note
FEDh POSTDEC0
FECh
FFEh
FFDh
FFCh
FFBh
FEFh
FEEh
FEBh
FEAh
FFFh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FE9h
FE8h
FE7h
FE6h
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
1:
2:
3:
4:
POSTINC0
POSTINC1
PREINC0
PREINC1
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
WREG
FSR1H
FSR0L
FSR1L
This is not a physical register.
This register is not available on 64-pin devices.
This register shares the same address with another register (see Table 5-4 for alternate register).
PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master
modes and PMDOUTx is used in Slave modes.
SPECIAL FUNCTION REGISTERS
TOSU
TOSH
Name
TOSL
BSR
PCL
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J50 FAMILY DEVICES
Address
FDDh POSTDEC2
FDCh
FCDh
FCCh
FDFh
FDEh
FDBh
FDAh
FCFh
FCEh
FCBh
FCAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
POSTINC2
OSCCON
PREINC2
SSP1CON1
SSP1CON2
PLUSW2
ADCON0
ADCON1
SSP1STAT
SSP1ADD
SSP1BUF
WDTCON
CM1CON
CM2CON
TMR1H
T1CON
TMR1L
ADRESH
ADRESL
INDF2
STATUS
TMR2
TMR0H
T0CON
T2CON
FSR2H
FSR2L
TMR0L
RCON
PR2
Name
(3)
(1)
(3)
(3)
(3)
(3)
(1)
(3)
(3)
(1)
(3)
(1)
(1)
Address
FBDh
FBCh
FBFh
FBEh ECCP1DEL
FBBh
FBAh
FAEh
FADh
FACh
FABh
FAAh
FB9h ECCP2DEL
FB8h
FB7h
FB6h
FB5h
FB4h ECCP3DEL
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA2h
FA1h
FA0h
FA3h
CCP1CON
CCP2CON
CCP3CON
ECCP1AS
ECCP2AS
ECCP3AS
CCPR1H
CCPR2H
CCPR3H
SPBRG1
RCREG1
SPBRG2
RCREG2
TXREG2
EECON2
EECON1
CCPR1L
CCPR2L
CCPR3L
TXREG1
RCSTA1
TXSTA1
TXSTA2
Name
IPR3
PIR3
IPR2
PIR2
PIE2
PIE3
Address
PIC18F87J50 FAMILY
F9Eh
F9Dh
F9Ch
F9Bh
F9Ah
F8Eh
F8Dh
F8Ch
F8Bh
F8Ah
F9Fh
F8Fh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
ALU’s STATUS register is described later in this
section. Registers related to the operation of the
peripheral features are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s
Note:
OSCTUNE
PORTH
PORTJ
TRISH
RCSTA2
TRISJ
LATH
PORTG
PORTE
PORTD
PORTC
PORTB
LATJ
PORTF
PORTA
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA
Name
LATG
LATD
LATC
LATB
LATF
LATE
LATA
IPR1
PIR1
PIE1
(2)
(2)
(2)
(2)
(2)
(2)
Addresses, F40h through F5Fh, are not
part of the Access Bank, therefore specify-
ing a BSR should be used to access these
registers.
Address
F7Dh
F7Ch
F6Dh
F6Ch
F7Eh
F7Bh
F7Ah
F6Eh
F6Bh
F6Ah
F7Fh
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h
F61h
F60h
PMADDRH
PMADDRL
BAUDCON1
BAUDCON2
SSP2CON1
SSP2CON2
CCP4CON
CCP5CON
SSP2STAT
SPBRGH1
SPBRGH2
SSP2ADD
SSP2BUF
PMDIN1H
PMDIN1L
CCPR4H
CCPR5H
CCPR4L
CCPR5L
CMSTAT
UFRMH
TMR3H
T3CON
T4CON
UFRML
TMR3L
USTAT
PR4
UCON
Name
TMR4
UEIR
UIR
(3)
(4)
(4)
Address
DS39775C-page 81
F5Dh
F5Ch
F4Dh
F4Ch
F5Fh
F5Eh
F5Bh
F5Ah
F4Fh
F4Eh
F4Bh
F4Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F49h
F48h
F47h PMDOUT2H
F46h PMDOUT2L
F45h
F44h
F43h
F42h
F41h
F40h
PMMODEH
PMMODEL
PMSTATH
PMCONH
PMDIN2H
PMSTATL
PMCONL
PMDIN2L
UADDR
UEP15
UEP14
UEP13
UEP12
UEP10
UEP11
Name
UCFG
PMEH
PMEL
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UEIE
UIE