PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 210

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
17.1
Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.
17.1.1
The ECCP/CCP modules utilize Timers 1, 2, 3 or 4,
depending on the mode selected. Timer1 and Timer3
are available to modules in Capture or Compare
modes, while Timer2 and Timer4 are available for
modules in PWM mode.
TABLE 17-1:
FIGURE 17-1:
DS39775C-page 210
Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may
resource as a common time
base.
Timer3 and Timer4 are not
available.
ECCP1
ECCP2
ECCP3
TMR1
CCP4
CCP5
TMR2
T3CCP<2:1> = 00
CCP Mode
Compare
share
Capture
CCP Module Configuration
PWM
CCP MODULES AND TIMER
RESOURCES
either
CCP MODE – TIMER
RESOURCE
TMR3
TMR4
ECCP/CCP AND TIMER INTERCONNECT CONFIGURATIONS
timer
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for ECCP1
only (depending on selected
mode).
All other modules use either
Timer3 or Timer4. Modules
may
resource as a common time
base
Capture/Compare or PWM
modes.
Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4
Timer Resource
ECCP1
TMR1
TMR2
T3CCP<2:1> = 01
share
if
they
either
ECCP2
ECCP3
TMR3
TMR4
CCP4
CCP5
are
timer
in
Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for ECCP1
and ECCP2 only (depending
on the mode selected for each
module). Both modules may
use a timer as a common time
base if they are both in
Capture/Compare or PWM
modes.
The other modules use either
Timer3 or Timer4. Modules
may
resource as a common time
base
Capture/Compare or PWM
modes.
The assignment of a particular timer to a module is
determined by the timer to CCP enable bits in the
T3CON register (Register 15-1, page 203). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 17-1.
17.1.2
When operating in Output mode (i.e., in Compare or
PWM modes), the drivers for the CCPx pins can be
optionally configured as open-drain outputs. This fea-
ture allows the voltage level on the pin to be pulled to
a higher level through an external pull-up resistor, and
allows the output to communicate with external cir-
cuits without the need for additional level shifters. For
more information, see Section 10.1.4 “Open-Drain
Outputs”.
The open-drain output option is controlled by the bits in
the ODCON1 register. Setting the appropriate bit con-
figures the pin for the corresponding module for
open-drain operation. The ODCON1 memory shares
the same address space as TMR1H. The ODCON1
register can be accessed by setting the ADSHR bit in
the WDTCON register(WDTCON<4>).
ECCP1
ECCP2
TMR1
TMR2
T3CCP<2:1> = 10
share
if
they
either
OPEN-DRAIN OUTPUT OPTION
ECCP3
TMR3
TMR4
CCP4
CCP5
are
timer
in
© 2009 Microchip Technology Inc.
Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may
resource as a common time
base.
Timer1 and Timer2 are not
available.
TMR1
TMR2
T3CCP<2:1> = 11
share
either
ECCP1
ECCP2
ECCP3
TMR3
TMR4
CCP4
CCP5
timer