PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 188

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
11.4
This section introduces some potential applications for
the PMP module.
FIGURE 11-27:
11.4.2
Partial multiplexing implies using more pins; however,
for a few extra pins, some extra performance can be
achieved. Figure 11-28 shows an example of a mem-
FIGURE 11-28:
FIGURE 11-29:
DS39775C-page 188
Application Examples
PIC18F
PIC18F
PIC18F
PARTIALLY MULTIPLEXED
MEMORY OR PERIPHERAL
PMA<14:7>
PMD<7:0>
PMD<7:0>
PMD<7:0>
PMALH
PMALL
PMALL
PMWR
PMWR
PMRD
PMALL
PMRD
PMCS
PMCS
PMWR
PMRD
PMCS
EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION
EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION
EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION
A<14:8>
AD<7:0>
ALE
CS
RD
WR
373
373
373
Parallel Peripheral
A<15:8>
D<7:0>
D<7:0>
A<7:0>
A<7:0>
11.4.1
Figure 11-27 demonstrates the hookup of a memory or
another addressable peripheral in Full Multiplex mode.
Consequently, this mode achieves the best pin saving
from the microcontroller perspective. However, for this
configuration, there needs to be some external latches
to maintain the address.
ory or peripheral that is partially multiplexed with an
external latch. If the peripheral has internal latches, as
shown in Figure 11-29, then no extra circuitry is
required except for the peripheral itself.
MULTIPLEXED MEMORY OR
PERIPHERAL
A<14:0>
D<7:0>
CE
A<15:0>
D<7:0>
CE
OE
OE
WR
WR
© 2009 Microchip Technology Inc.
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines
Address Bus
Data Bus
Control Lines