PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 224

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
18.4.4
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The PWM output
signal is output on the P1A pin, while the complemen-
tary PWM output signal is output on the P1B pin
(Figure 18-4). This mode can be used for half-bridge
applications, as shown in Figure 18-5, or for full-bridge
applications, where four power switches are being
modulated with two PWM signals.
In Half-Bridge Output mode, the programmable
dead-band delay can be used to prevent shoot-through
current in half-bridge power devices. The value of bits
P1DC6:P1DC0 sets the number of instruction cycles
before the output is driven active. If the value is greater
than the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 18.4.6
“Programmable Dead-Band Delay” for more details
on dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTC<2> and PORTE<6> data latches, the
TRISC<2> and TRISE<6> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 18-5:
DS39775C-page 224
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
PIC18F87J50
P1A
P1B
PIC18F87J50
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
FIGURE 18-4:
Note 1: At this time, the TMR2 register is equal to the
P1A
P1B
td = Dead Band Delay
(2)
(2)
2: Output signals are shown as active-high.
(1)
Load
V+
PR2 register.
V-
Duty Cycle
V+
td
V-
Period
Load
td
HALF-BRIDGE PWM
OUTPUT
© 2009 Microchip Technology Inc.
FET
Driver
FET
Driver
(1)
+
V
-
+
V
-
Period
(1)