PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet
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PIC18F86J50T-I/PT Summary of contents
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... Flash USB Microcontrollers © 2009 Microchip Technology Inc. PIC18F87J50 Family Data Sheet 64/80-Pin High-Performance, with nanoWatt Technology DS39775C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... I C™ Master and Slave modes • 8-Bit Parallel Master Port/Enhanced Parallel Slave Port with 16 Address Lines • Dual Analog Comparators with Input Multiplexing © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Peripheral Highlights (continued): • 10-Bit 12-Channel Analog-to-Digital (A/D) Converter module: ...
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... The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit. DS39775C-page 4 MSSP CCP/ 10-Bit I/O ECCP Master A/D (ch) SPI (PWM C™ PIC18F6XJ5X RB0/FLT0/INT0 47 RB1/INT1/PMA4 46 RB2/INT2/PMA3 45 RB3/INT3/PMA2 44 RB4/KBI0/PMA1 43 RB5/KBI1/PMA0 42 RB6/KBI2/PGC OSC2/CLKO/RA6 39 OSC1/CLKI/RA7 RB7/KBI3/PGD 36 RC5/SDO1/C2OUT 35 RC4/SDI1/SDA1 34 RC3/SCK1/SCL1 33 RC2/ECCP1/P1A © 2009 Microchip Technology Inc. ...
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... The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. 3: PMP pin placement when PMPMX = 1. 4: PMP pin placement when PMPMX = 0. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY ...
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... Electrical Characteristics .......................................................................................................................................................... 419 29.0 Packaging Information.............................................................................................................................................................. 459 Appendix A: Revision History............................................................................................................................................................. 463 Appendix B: Device Differences......................................................................................................................................................... 463 The Microchip Web Site ..................................................................................................................................................................... 477 Customer Change Notification Service .............................................................................................................................................. 477 Customer Support .............................................................................................................................................................................. 477 Reader Response .............................................................................................................................................................................. 478 Product Identification System............................................................................................................................................................. 479 DS39775C-page 6 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY DS39775C-page 7 ...
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... PIC18F87J50 FAMILY NOTES: DS39775C-page 8 © 2009 Microchip Technology Inc. ...
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... Universal Serial Bus communications module with a built-in transceiver that is compliant with the USB Specification Revision 2.0. The module supports both low-speed and full-speed communication for all supported data transfer types. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 1.1.3 OSCILLATOR OPTIONS AND FEATURES ...
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... I/O ports (7 bidirectional ports on 64-pin devices, 9 bidirectional ports on 80-pin devices). All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for all devices are listed in Table 1-3 and Table 1-4. © 2009 Microchip Technology Inc. devices to ...
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... I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules Serial Communications Parallel Communications (PMP) 10-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY PIC18F65J50 PIC18F66J50 DC – 48 MHz DC – 48 MHz 32K 64K 16384 32768 3904 ...
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... Timer4 CCP4 CCP5 EUSART2 EUSART1 PORTA Data Latch (1) RA0:RA5 (3.9 Kbytes) 12 PORTB (1) RB0:RB7 12 4 Access Bank 12 PORTC (1) RC0:RC7 logic PORTD (1) RD0:RD7 8 PRODH PRODL PORTE (1) RE0:RE7 Multiply PORTF 8 8 (1) RF2:RF7 ALU<8> 8 PORTG (1) RG0:RG4 Comparators MSSP1 MSSP2 USB © 2009 Microchip Technology Inc. ...
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... PMP ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Data Latch 8 8 Data Memory (3.9 Kbytes) PCLATU PCLATH Address Latch ...
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... In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL System cycle clock output (F General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description /4). OSC ) DD © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port ...
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... I/O ST Synchronous serial clock input/output for I I/O ST Digital I/O. I/O TTL Parallel Master Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description 2 C mode © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port ...
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... Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I Analog Comparator 1 input A. I/O ST Digital I/O. I TTL SPI slave select input. O TTL Comparator 1 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. 2: Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared. 3: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port ...
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... In RC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL System cycle clock output (F General purpose I/O pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description /4). OSC ) DD © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTA is a bidirectional I/O port. ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... SPI data out. I/O ST Digital I/O. I/O TTL External memory address/data 5. I/O TTL Parallel Master Port data SPI data in C™ data I/O. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port (continued). ...
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... ECCP3 PWM output B. I/O ST Digital I/O. I/O TTL External memory address/data 13. O — Parallel Master Port address. O — ECCP1 PWM output C. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port (continued). ...
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... Analog input 11. I Analog Comparator 1 input A. I/O ST Digital I/O. I/O TTL Parallel Master Port address. I TTL SPI slave select input. O — Comparator 1 output. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). 6: Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... I/O ST Digital I/O. I/O — Parallel Master Port read strobe. I Analog Analog input 14. O — ECCP1 PWM output C. I Analog Comparator 1 input C. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... Pin placement when PMPMX = 1. 7: Pin placement when PMPMX = 0. 8: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Pin Buffer Type Type PORTH is a bidirectional I/O port (continued). ...
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... Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). P — USB voltage input pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Description ) DD © 2009 Microchip Technology Inc. ...
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... RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output will stop when in Sleep mode, but will continue during Idle mode (see Figure 2-1). © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY TABLE 2-1: OSCILLATOR MODES Mode ...
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... MHz ÷ 2 FSEN 1 USB Module Clock Needs 48 MHz for FS ÷ Needs 6 MHz for LS 0 ÷ CPDIV1:CPDIV0 Primary Clock IDLE (4) Source CPU 00 (3) Peripherals 01 RA6 11 ÷ 4 OSCCON<1:0> CLKO Enabled Modes WDT, PWRT, FSCM and Two-Speed Start-up © 2009 Microchip Technology Inc. ...
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... See the notes following Table 2-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY TABLE 2-3: Osc Type HS Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Watchdog Timer • Two-Speed Start-up These features are discussed in greater detail in Section 25.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 44). © 2009 Microchip Technology Inc. ...
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... The low-frequency INTRC oscillator operates indepen- dently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 2.2.5.3 Compensating for INTOSC Drift It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register ...
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... See Table 2-4 and Table 2-5 for possible combinations which can be used for low-speed USB operation. TABLE 2-4: CLOCK FOR LOW-SPEED USB Clock CPU CPDIV<1:0> Input Clock R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown USB Clock <1, 1> 48 MHz <1, 0> 24 MHz © 2009 Microchip Technology Inc. ...
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... All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz). Note 1: Only valid for low-speed USB operation. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Clock Mode MCU Clock Division (FOSC2:FOSC0) ...
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... The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed. Oscillator Frequency Select bits, © 2009 Microchip Technology Inc. ...
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... It is recommended that the Timer1 oscillator be operating and stable prior to switching the clock source; other- wise, a very long delay may occur while the Timer1 oscillator starts. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 2.4.2 OSCILLATOR TRANSITIONS PIC18F87J10 family devices contain circuitry to prevent clock “glitches” when switching between clock sources ...
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... Default output frequency of INTOSC on Reset (4 MHz). 4: Source selected by the INTSRC bit (OSCTUNE<7>), see text. DS39775C-page 44 (1) (2) R/W-0 R-1 U-1 IRCF0 OSTS — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (4) (2) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on RE3 when the device is in Sleep mode ...
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... This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC or internal oscillator modes are used as the primary clock source. consumption are listed in (parameter 38, CSD © 2009 Microchip Technology Inc. ...
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... RC_IDLE 1 11 Note 1: IDLEN reflects its value when the SLEEP instruction is executed. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • The primary clock source, as defined by the FOSC2:FOSC0 Configuration bits • ...
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... SEC_RUN mode is entered by setting the SCS1:SCS0 bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 3-1), the primary oscilla- tor is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-2) ...
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... The IDLEN and SCS bits are not affected by the switch. The INTRC block source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. block (see n-1 n Clock Transition PLL ( n-1 n Clock Transition OSTS Bit Set © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J50 FAMILY NOTES: DS39775C-page 54 © 2009 Microchip Technology Inc. ...
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... Ripple Counter Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to function properly. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1 ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39775C-page 56 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... BOR running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V rises above V , the Power-up Timer will execute the BOR additional time delay. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY FIGURE 4- Note 1: External Power-on Reset circuit is required ...
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... PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure 4-5). This is useful for testing purposes synchronize more than one PIC18FXXXX device operating in parallel PWRT T PWRT © 2009 Microchip Technology Inc RISE < PWRT ): CASE 1 DD ...
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... FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY T PWRT , V RISE > 3. PWRT ): CASE ...
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... Reset. Table 4-2 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register ( POR STKPTR Register BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu (3) uuuu uuuu uuuu uuuu uuuu uuuu (3) uuuu uuuu uuuu uuuu uuuu uuuu ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction ...
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... Microchip Technology Inc. Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuu- -uuu uuu- u--u uuuu ...
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... When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY MCLR Resets WDT Reset Power-on Reset, RESET Instruction ...
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... PIC18F87J50 FAMILY NOTES: DS39775C-page 68 © 2009 Microchip Technology Inc. ...
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... Unimplemented Read as ‘0’ Read as ‘0’ Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 5.1 Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-Mbyte program memory space ...
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... Section 25.1 “Configuration Bits”. TABLE 5-1: FLASH CONFIGURATION WORD FOR PIC18F87J50 FAMILY DEVICES Program Configuration Device Memory (Kbytes) PIC18F65J50 32 7FF8h to 7FFFh PIC18F85J50 PIC18F66J50 64 FFF8h to FFFFh PIC18F86J50 PIC18F66J55 96 PIC18F86J55 PIC18F67J50 128 PIC18F87J50 © 2009 Microchip Technology Inc. through Word Addresses 17FF8h to 17FFFh 1FFF8h to 1FFFFh ...
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... Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ Note 1: Implemented only on 80-pin devices. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The Microcontroller mode is also the only operating mode available to 64-pin devices. • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block ...
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... Yes Yes Yes (2) with Address Shifting On-Chip Memory Space 000000h On-Chip Program Memory (Top of Memory) (3) (Top of Memory Mapped to External Memory 1FFFFFh – Space (Top of Memory) 1FFFFFh Table Read Table Write From To No Access No Access Yes Yes © 2009 Microchip Technology Inc. ...
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... TOSH TOSL 00h 1Ah 34h © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 SP1 SP0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write Execute INST (PC) Execute INST ( Fetch INST ( Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch Internal Phase Clock Fetch INST ( Flush (NOP) Fetch SUB_1 Execute SUB_1 © 2009 Microchip Technology Inc. ...
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... MOVFF 1111 0100 0101 0110 0010 0100 0000 0000 ADDWF © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. © 2009 Microchip Technology Inc. ...
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... Note 1: These banks also serve as RAM buffers for USB operation. See Section 5.3.1 “USB RAM” for more information. 2: Addresses, F40h through F5Fh, are not part of the Access Bank, therefore, specifying a BSR should be used to access these registers. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Data Memory Map ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. (2) From Opcode © 2009 Microchip Technology Inc. ...
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... PMADDRH and PMDOUTH share the same address and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral ...
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... PR2 (1) (A) MEMCON R/W-0 U-0 U-0 ADSHR — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Address Name FC2h (D) ADCON0 (A) ANCON1 FC1h (D) ADCON1 (A) ANCON0 F77h (D) PR4 (A) CVRCON U-0 U-0 — SWDTEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 ...
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... GO/DONE ADON 63, 301 0000 0000 — — 63, 301 0000 00-- ADCS1 ADCS0 63, 301 0000 0000 PCFG1 PCFG0 63, 301 0--0 0000 — SWDTEN 0x-0 ---0 63, 358 2 C™ Slave mode. See Section 19.4.3.2 “Address © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 ...
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... TMR3CS TMR3ON 65, 208 0000 0000 65, 207 0000 0000 65, 208 1111 1111 CVR1 CVR0 65, 346 0000 0000 T4CKPS1 T4CKPS0 -000 0000 65, 207 2 C™ Slave mode. See Section 19.4.3.2 “Address © 2009 Microchip Technology Inc. ...
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... The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 ...
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... PTEN9 PTEN8 67, 171 0000 0000 PTEN1 PTEN0 0000 0000 67, 172 IB1F IB0F 67, 172 00-- 0000 OB1E OB0E 67, 173 10-- 1111 2 C™ Slave mode. See Section 19.4.3.2 “Address © 2009 Microchip Technology Inc. ...
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... For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY register then reads back as ‘000u u1uu’ recom- ...
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... EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. Stack Pointer ...
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... FCCh. This means the contents of location FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY mapped in the SFR space but are not physically imple- mented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. ...
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... Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 5.2.4 “Two-Word Instructions”. © 2009 Microchip Technology Inc. ...
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... The use of the Access Bank is forced (‘a’ = 0); and • The file address argument is less than or equal to 5Fh. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing 8-bit address in the Access Bank ...
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... FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 060h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h Valid range for ‘f’ FFh ffffffff FSR2L ffffffff ...
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... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F87J50 FAMILY NOTES: DS39775C-page 96 © 2009 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... Reset write operation was Reading attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
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... The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-x R/W-0 (1) FREE ...
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... TBLPTR based on Flash program memory operations. AND TBLRD TBLWT Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write TBLPTRH 8 7 TABLE READ: TBLPTR<21:0> INSTRUCTIONS TBLPTRL 0 © 2009 Microchip Technology Inc. ...
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... WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... The CPU will stall for duration of the erase for T (see parameter D133A Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
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... Write the 64 bytes into the holding registers with auto-increment. 7. Set the WREN bit (EECON1<2>) to enable byte writes. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device ...
Page 104
... TBLWT holding register. ; loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; re-enable interrupts ; disable write to memory ; done with one write cycle ; if not done replacing the erase block © 2009 Microchip Technology Inc. ...
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... MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WPROG BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 3. Set the WREN bit (EECON1<2>) to enable writes and the WPROG bit (EECON1<5>) to select Word Write mode. 4. Disable interrupts. 5. Write 55h to EECON2. ...
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... See Section 25.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 4 Bit 3 Bit 2 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF FREE WRERR WREN Reset Bit 1 Bit 0 Values on Page INT0IF RBIF — 63 © 2009 Microchip Technology Inc. ...
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... Note: For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
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... ADSHR bit in the Register 25-9). R/W-0 U-0 U-0 WAIT0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared WDTCON register (see R/W-0 R/W-0 WM1 WM0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F87J50 FAMILY 7.2.1 ADDRESS SHIFTING ON THE EXTERNAL BUS By default, the address presented on the external bus is the value of the PC. In practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller ...
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... BA0 for the byte address line and one I/O line to select between Byte and Word mode. The other 16-bit modes do not need BA0. JEDEC standard static RAM memories will use the signals for byte selection. © 2009 Microchip Technology Inc. are affected; A19:A16 the ...
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... Upper order address lines are used only for 20-bit address widths. 2: This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY During a TBLWT instruction cycle, the TABLAT data is presented on the upper and lower bytes of the AD15:AD0 bus ...
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... The obvious limitation to this method is that the table write must be done in pairs on a specific word even address boundary to correctly write a word location. A<20:1> 373 D<15:0> 373 cycle to an odd address JEDEC Word A<x:0> EPROM Memory D<15:0> ( Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 114
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 0E55h 3AABh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The Address Latch Enable (ALE) pin indicates that the address bits, AD<15:0>, are available on the external memory interface bus ...
Page 116
... Opcode Fetch TBLRD 92h MOVLW 55h from 199E67h from 000102h TBLRD Cycle 1 TBLRD Cycle 00h 3Ah 55h ABh 0Eh Opcode Fetch Sleep Mode, MOVLW 55h from 007556h SLEEP Opcode Fetch ADDLW 55h from 000104h MOVLW Bus Inactive © 2009 Microchip Technology Inc. ...
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... If operations in a lower power Run mode are anticipated, users should provide in their applications for adjusting memory access times at the lower clock speeds. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended ...
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... PIC18F87J50 FAMILY NOTES: DS39775C-page 118 © 2009 Microchip Technology Inc. ...
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... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL ...
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... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
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... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are ...
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... IPEN PEIE/GIEL IPEN TMR0IF IPEN TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP © 2009 Microchip Technology Inc. Wake- Idle or Sleep modes Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL ...
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... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Note: Interrupt flag bits are set when an interrupt ...
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... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39775C-page 124 R/W-1 R/W-1 R/W-1 INTEDG2 INTEDG3 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 INT3IP RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 ...
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... R-0 R/W-0 R/W-0 TX1IF SSP1IF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared should ensure the R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... A TMR1/TMR3 register capture occurred (must be cleared in software TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 USBIF BCL1IF LVDIF U = Unimplemented bit, read as ‘ ...
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... A TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. DS39775C-page 128 R/W-0 R/W-0 R/W-0 TX2IF TMR4IF CCP5IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 CCP4IF CCP3IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
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... TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled DS39775C-page 130 R/W-0 R/W-0 R/W-0 USBIE BCL1IE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TMR3IE CCP2IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
Page 132
... Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority DS39775C-page 132 R/W-1 R/W-1 R/W-1 TX1IP SSP1IP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-1 R/W-1 R/W-1 USBIP BCL1IP LVDIP U = Unimplemented bit, read as ‘0’ ...
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... Low priority bit 0 CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority DS39775C-page 134 R/W-1 R/W-1 R/W-1 TX2IP TMR4IP CCP5IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 CCP4IP CCP3IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘ ...
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... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
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... TRIS Latch RD TRIS PORT © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 10.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 10 ...
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... By default, these PMP inputs use the port’s ST buffers. As with the ODCON registers, the PADCFG1 register resides in the SFR configuration space; it shares the same memory address as the TMR2 register. PADCFG1 is accessed by setting the ADSHR bit (WDTCON<4>). © 2009 Microchip Technology Inc. 5V ...
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... Value at POR ‘1’ = Bit is set bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 SPI2OD:SPI1OD: SPI Open-Drain Output Enable bits 1 = Open-drain output on SDOx pin enabled 0 = Open-drain output disabled © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 R/W-0 CCP5OD CCP4OD ECCP3OD U = Unimplemented bit, read as ‘ ...
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... I/O = digital OSC INITIALIZING PORTA ; Initialize PORTA by ; clearing output ; data latches ; Alternate method to ; clear data latches ; the shared SFR ; Configure A/D ; for digital inputs ; to the shared SFR ; Value used to ; initialize ; data direction ; Set RA<3:0> as inputs, ; RA<5:4> as outputs © 2009 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: When PMPMX = 0. 2: Available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type ...
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... Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> DS39775C-page 142 Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 RA3 RA2 LATA5 LATA4 LATA3 LATA2 TRISA5 TRISA4 TRISA3 TRISA2 — PCFG4 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on Page: RA1 RA0 65 LATA1 LATA0 64 TRISA1 TRISA0 64 PCFG1 PCFG0 63 © 2009 Microchip Technology Inc. ...
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... Clear flag bit, RBIF. A mismatch condition will continue to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF cleared. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature ...
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... LATB<7> data output. I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-pin change. O DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation. Description (2) (2) (2) © 2009 Microchip Technology Inc. ...
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... TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 LATB5 LATB4 ...
Page 146
... EXAMPLE 10-3: INITIALIZING PORTC CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches CLRF LATC ; Alternate method to clear ; output data latches MOVLW 0CFh ; Value used to initialize ; data direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs © 2009 Microchip Technology Inc. ...
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... O = Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: Default assignment for ECCP2/P2A when CCP2MX Configuration bit is set. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O Description ...
Page 148
... Synchronous serial data input (EUSART1 module). User must configure as an input. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 Description Reset Bit 1 Bit 0 Values on Page: RC1 RC0 65 LATC1 LATC0 64 TRISC1 TRISC0 64 © 2009 Microchip Technology Inc. ...
Page 149
... Port is active, the input buffers are TTL. For more information, refer to Section 11.0 “Parallel Master Port” © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Each of the PORTD pins has a weak internal pull-up. The pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up ...
Page 150
... Parallel Master Port data input SPI data input (MSSP2 module DIG I C™ data output (MSSP2 module); takes priority over port data data input (MSSP2 module); input type depends on module setting. Description (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) © 2009 Microchip Technology Inc. ...
Page 151
... LATD LATD7 LATD6 TRISD TRISD7 TRISD6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTD. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATD<6> data output PORTD<6> data input. O DIG-3 External memory interface, address/data bit 6 output ...
Page 152
... Output”. EXAMPLE 10-5: INITIALIZING PORTE ; CLRF PORTE Initialize PORTE by ; clearing output ; data latches CLRF LATE ; Alternate method to clear ; output data latches ; MOVLW 03h Value used to initialize ; data direction ; MOVWF TRISE Set RE<1:0> as inputs ; RE<7:2> as outputs © 2009 Microchip Technology Inc. ...
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... External memory interface I/O takes priority over all other digital and PMP I/O. 3: Available on 80-pin devices only. 4: Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller mode). 5: Default configuration for PMP (PMPMX Configuration bit = 1). © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATE<0> data output. ...
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... Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 LATE5 LATE4 LATE3 LATE2 TRISE5 TRISE4 TRISE3 TRISE2 (1) RJPU RG4 RG3 RG2 Description (2) (2) (2) (2) (2) (2) Reset Bit 1 Bit 0 Values on Page: RE1 RE0 65 LATE1 LATE0 64 TRISE1 TRISE0 64 RG1 RG0 65 © 2009 Microchip Technology Inc. ...
Page 155
... To configure PORTF as digital I/O, set the corresponding bits in ANCON0 and ANCON1. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY When Configuration bit, PMPMX = 0, PORTF is multi- plexed with Parallel Master data port. This multiplexing is available only in 80 pin devices. ...
Page 156
... POR; does not affect digital output. I ANA Comparator 1 input A. O DIG LATF<7> data output PORTF<7> data input. O DIG Parallel Master Port data out. I TTL Parallel Master Port data input. I TTL Slave select input for MSSP1. O DIG Comparator 1 output. Description © 2009 Microchip Technology Inc. ...
Page 157
... ANCON1 PCFG15 PCFG14 PCFG13 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. Note 1: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RF5 ...
Page 158
... EXAMPLE 10-7: INITIALIZING PORTG CLRF PORTG ; Initialize PORTG by ; clearing output ; data latches CLRF LATG ; Alternate method to clear ; output data latches MOVLW 04h ; Value used to initialize ; data direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as outputs © 2009 Microchip Technology Inc. ...
Page 159
... O 0 Legend Output Input, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O Type DIG LATG<0> data output. ...
Page 160
... Unimplemented on 64-pin devices, read as ‘0’. DS39775C-page 160 Bit 5 Bit 4 Bit 3 Bit 2 (1) RJPU RG4 RG3 RG2 — LATG4 LATG3 LATG2 — TRISG4 TRISG3 TRISG2 Reset Bit 1 Bit 0 Values on Page: RG1 RG0 65 LATG1 LATG0 64 TRISG1 TRISG0 64 © 2009 Microchip Technology Inc. ...
Page 161
... ANCON1 register. RH3 to RH6 is multiplexed with Parallel Master Port and RH4 to RH6 are multiplexed as comparator pins. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY PORTH can also be configured as the alternate Enhanced PWM output channels B and C for the ECCP1 and ECCP3 modules ...
Page 162
... A/D input channel 14. Default input configuration on POR; does not affect digital output. DIG ECCP1 Enhanced PWM output, channel C; takes priority over port and PMP data. May be configured for tri-state during Enhanced PWM shutdown events. ANA Comparator 1 input C. © 2009 Microchip Technology Inc. ...
Page 163
... PCFG15 PCFG14 Legend: Shaded cells are not used by PORTH. Note 1: Unimplemented on 64-pin devices, read as ‘0’. 2: Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O Type DIG LATH<7> data output. ST PORTH< ...
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... EXAMPLE 10-9: INITIALIZING PORTJ CLRF PORTJ ; Initialize PORTG by ; clearing output ; data latches CLRF LATJ ; Alternate method to clear ; output data latches MOVLW 0CFh ; Value used to initialize ; data direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs © 2009 Microchip Technology Inc. ...
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... LATJ6 (1) TRISJ TRISJ7 TRISJ6 TRISJ5 PORTG RDPU REPU RJPU Legend: Shaded cells are not used by PORTJ. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output ...
Page 166
... PIC18F87J50 FAMILY NOTES: DS39775C-page 166 © 2009 Microchip Technology Inc. ...
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... Parallel Master Port Parallel Slave Port. FIGURE 11-1: PMP MODULE OVERVIEW PIC18 Parallel Master Port © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Key features of the PMP module include: • Programmable Address Lines • Two Chip Select Lines • Programmable Strobe Options - Individual Read and Write Strobes or ...
Page 168
... R/W-0 R/W-0 R/W-0 ADRMUX1 ADRMUX0 PTBEEN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (Register 11-1 and registers (Register 11-3 and (Register 11-5 and R/W-0 R/W-0 PTWREN PTRDEN bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 169
... Read strobe active-high (PMRD Read strobe active-low (PMRD) For Master Mode 1 (PMMODEH<1:0> Read/write strobe active-high (PMRD/PMWR Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY (1) (1) (1) R/W-0 R/W-0 ...
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... Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD<7:0>) DS39775C-page 170 R/W-0 R/W-0 R/W-0 INCM1 INCM0 MODE16 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 MODE1 MODE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 5-0 PTEN13:PTEN8: PMP Address Port Enable bits 1 = PMA<13:8> function as PMP address lines 0 = PMA<13:8> function as port I/O © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY R/W-0 R/W-0 WAITM2 WAITM1 WAITM0 U = Unimplemented bit, read as ‘ ...
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... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R-0 R-0 — IB3F IB2F U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PTEN1 PTEN0 bit Bit is unknown R-0 R-0 IB1F IB0F bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit Output buffer contains data that has not been transmitted © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY U-0 R-1 R-1 — ...
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... PADCFG1 is accessed by setting the ADSHR bit (WDTCON<4>). Refer to Section 5.3.5.1 “Shared Address SFRs” for more information. (1) R/W-0 R/W-0 R/W-0 ADDR<13:8> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS PMRD PMWR © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is con- figured using the MODE1:MODE0 bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master and it determines the usage of the control pins ...
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... READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUTL1 register (PMDOUTL1<7:0>) is presented onto PMD<7:0>.The timing for the control signals in Read mode is shown in Figure 11- © 2009 Microchip Technology Inc ...
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... PMCS PMRD PMWR Data Bus Control Lines © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY flow is generated, and the Buffer Overflow flag bit OBUF is set. If all four OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. ...
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... PMDOUT1L (0) 00 PMDOUT1H (1) 01 PMDOUT2L (2) 10 PMDOUT2H((3) 11 PIC18F Slave PMA<1:0> Write Read PMD<7:0> Address Address Decode Decode PMDOUT1L (0) PMCS1 PMDOUT1H (1) PMDOUT2L (2) PMRD PMDOUT2H (3) PMWR © 2009 Microchip Technology Inc. Input Register (Buffer) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) ...
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... PMRD PMD<7:0> PMA<1:0> IBF PMPIF © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. The OBxE flag bit is set when all the buffers are empty. If any buffer is already empty, OBxE = 1, the next read to that buffer will generate an OBUF event ...
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... During the second cycle, the upper eight bits of the address are presented on the PMD<7:0> pins with the PMALH strobe active. In the event the upper address bits are configured as chip select corresponding address bits are automatically forced to ‘0’. © 2009 Microchip Technology Inc. and pins, the ...
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... PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC18F © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY PMA<13:0> PMD<7:0> PMCS1 PMCS2 Address Bus ...
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... PMDIN1L register will not initiate either a read nor a write). 11.3.10.2 INTERRUPTS When the PMP module interrupt is enabled for Master mode, the module will interrupt on every completed read or write cycle; otherwise, the BUSY bit is available to query the status of the module. © 2009 Microchip Technology Inc. ...
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... FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMA<13:8> PMRD PMWR PMALL PMPIF BUSY WAITB<1:0> © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Data Data WAITE<1:0> WAITM<3:0> = 0010 ...
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... PMA<13:8> PMWR PMRD PMALL PMPIF BUSY WAITB<1:0> FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE PMCS2 PMCS1 PMD<7:0> Address<7:0> PMA<13:8> PMRD/PMWR PMENB PMALL PMPIF BUSY DS39775C-page 184 Data Data WAITE<1:0> WAITM<3:0> = 0010 Data © 2009 Microchip Technology Inc. ...
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... PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMWR PMRD PMALL PMALH PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Data Address<15:8> Data Address<15:8> Data ...
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... PMD<7:0> PMA<13:0> PMWR PMRD PMBE PMPIF BUSY FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS PMCS2 PMCS1 PMD<7:0> Address<7:0> PMA<13:8> PMWR PMRD PMBE PMALL PMPIF BUSY DS39775C-page 186 LSB MSB LSB MSB LSB MSB © 2009 Microchip Technology Inc. ...
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... PMRD PMBE PMALH PMALL PMPIF BUSY FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS PMCS2 PMCS1 Address<7:0> PMD<7:0> PMWR PMRD PMBE PMALH PMALL PMPIF BUSY © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY LSB MSB Address<15:8> LSB Address<15:8> LSB ...
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... Figure 11-29, then no extra circuitry is required except for the peripheral itself. A<7:0> 373 A<14:0> D<7:0> D<7:0> A<14:8> Parallel Peripheral AD<7:0> ALE Address Bus Data Bus Control Lines WR Address Bus Data Bus Control Lines Address Bus Data Bus Control Lines © 2009 Microchip Technology Inc. ...
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... Figure 11-32. In this case the PMP module is config- ured for active-high control signals since common LCD displays require active-high control. FIGURE 11-32: LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC18F PM<7:0> PMA0 PMRD/PMWR PMCS © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY Parallel EEPROM A<n:0> D<7:0> Parallel EEPROM A<n:1> ...
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... OB3E OB2E — — — Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 61 TMR2IF TMR1IF 64 TMR2IE TMR1IE 64 TMR2IP TMR1IP 64 66 WRSP RDSP MODE0 67 WAITE1 WAITE0 67 PTEN9 PTEN8 67 PTEN1 PTEN0 67 IB1F IB0F 67 OB1E OB0E 67 — — PMPTTL 62 © 2009 Microchip Technology Inc. ...
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... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TMR0ON T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87J50 FAMILY NOTES: DS39775C-page 194 © 2009 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Note 1: Default (legacy) SFR at this address, available when WDTCON<4> © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. ...
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... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
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... TIMER1 LP OSCILLATOR C1 PIC18F87J50 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF ...
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... Assuming that Timer1 is being used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator. In this case, one-half period of the clock is 15.25 μs. © 2009 Microchip Technology Inc. ...
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... F MOVLW .23 CPFSGT hours RETURN CLRF hours RETURN © 2009 Microchip Technology Inc. PIC18F87J50 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt ; Insert the next 4 lines of code when TMR1 ...
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... DS39775C-page 200 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF RC1IF TX1IF SSP1IF CCP1IF RC1IE TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Reset Bit 1 Bit 0 Values on Page: INT0IF RBIF 61 TMR2IF TMR1IF 64 TMR2IE TMR1IE 64 TMR2IP TMR1IP TMR1CS TMR1ON 62 © 2009 Microchip Technology Inc. ...