PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 50

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes while still executing code.
It works well for user applications which are not highly
timing sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting the SCS1:SCS0 bits
(OSCCON<1:0>) to ‘11’. When the clock source is
switched
Figure 3-3), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 3-3:
FIGURE 3-4:
DS39775C-page 50
Peripheral
Program
Counter
INTRC
OSC1
to
Note 1: T
Clock
Clock
RC_RUN MODE
CPU Clock
CPU
PLL Clock
Peripheral
Program
Counter
INTRC
Output
the
OSC1
Clock
Q1
OST
SCS1:SCS0 Bits Changed
internal
Q2
= 1024 T
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
PC
Q3
Q4
OSC
oscillator
; T
Q1
Q1
PLL
T
1
= 2 ms (approx). These intervals are not shown to scale.
OST (1)
PC
block
Q2
2
Clock Transition
3
T
OSTS Bit Set
PLL (1)
(see
Q3
PC + 2
Q4
n-1
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
block while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the OSTS bit is set and the primary
clock is providing the device clock. The IDLEN and
SCS bits are not affected by the switch. The INTRC
block source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
Q2
PC + 2
Q3
Q2
Q4
© 2009 Microchip Technology Inc.
Q3 Q4
Q1
Q1
PC + 4
Q2
Q2
PC + 4
Q3
Q3