PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 315

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

22.2.2.2
The PIC18F87J10 family devices have built-in pull-up
resistors designed to meet the requirements for
low-speed and full-speed USB. The UPUEN bit
(UCFG<4>) enables the internal pull-ups. Figure 22-1
shows the pull-ups and their control.
22.2.2.3
External pull-up may also be used. The V
used to pull up D+ or D-. The pull-up resistor must be
1.5 kΩ (±5%) as required by the USB specifications.
Figure 22-2 shows an example.
FIGURE 22-2:
© 2009 Microchip Technology Inc.
Note:
Note:
Microcontroller
PIC
The above setting shows a typical connection
for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.
The official USB specifications require that
USB devices must never source any cur-
rent onto the +5V V
cable. Additionally, USB devices must
never source any current on the D+ and D-
data lines whenever the +5V V
less than 1.17V. In order to meet this
requirement, applications which are not
purely bus powered should monitor the
V
module and the D+ or D- pull-up resistor
until V
be connected to and monitored by any 5V
tolerant I/O pin for this purpose.
®
BUS
Internal Pull-up Resistors
External Pull-up Resistors
V
USB
D+
D-
line and avoid turning on the USB
BUS
is greater than 1.17V. V
EXTERNAL CIRCUITRY
1.5 kΩ
BUS
Controller/HUB
line of the USB
USB
Host
BUS
pin may be
BUS
line is
can
PIC18F87J50 FAMILY
22.2.2.4
The usage of ping-pong buffers is configured using the
PPB1:PPB0 bits. Refer to Section 22.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
buffers.
22.2.2.5
An automatic eye pattern test can be generated by the
module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
meaning that the user is first responsible for configuring
the SIE clock settings, pull-up resistor and Transceiver
mode. In addition, the module has to be enabled.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note that this bit should never be set while the module
is connected to an actual USB system. This Test mode
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
the noise integrity of the USB signals which can be
affected by board traces, impedance mismatches and
proximity to other system components. It does not
properly test the transition from a receive to a transmit
state. Although the eye pattern is not meant to replace
the more complex USB certification test, it should aid
during first order system debugging.
Ping-Pong Buffer Configuration
Eye Pattern Test Enable
DS39775C-page 315