PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 247

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

REGISTER 19-6:
REGISTER 19-7:
© 2009 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-2
bit 1
bit 0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
Note 1:
GCEN
R/W-0
R/W-1
MSK7
bit 7
2:
If the I
(or writes to the SSPxBUF are disabled).
This register shares the same SFR address as SSPxADD, and is only addressable in select MSSP
operating modes. See Section 19.4.3.4 “7-Bit Address Masking Mode” for more details.
MSK0 is not used as a mask bit in 7-bit addressing.
GCEN: General Call Enable bit (Slave mode only)
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
ADMSK5:ADMSK2: Slave Address Mask Select bits (5-Bit Address Masking)
1 = Masking of corresponding bits of SSPxADD enabled
0 = Masking of corresponding bits of SSPxADD disabled
ADMSK1: Slave Address Least Significant bit(s) Mask Select bit
In 7-Bit Addressing mode:
1 = Masking of SSPxADD<1> only enabled
0 = Masking of SSPxADD<1> only disabled
In 10-Bit Addressing mode:
1 = Masking of SSPxADD<1:0> enabled
0 = Masking of SSPxADD<1:0> disabled
SEN: Start Condition Enable/Stretch Enable bit
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
MSK7:MSK0: Slave Address Mask Select bit
1 = Masking of corresponding bit of SSPxADD enabled
0 = Masking of corresponding bit of SSPxADD disabled
ACKSTAT
2
R/W-0
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
R/W-1
MSK6
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
SSPxMSK: I
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ADMSK5
R/W-0
R/W-1
MSK5
2
C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)
ADMSK4
R/W-0
R/W-1
MSK4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F87J50 FAMILY
ADMSK3
(1)
R/W-0
R/W-1
MSK3
ADMSK2
2
R/W-0
R/W-1
MSK2
C™ SLAVE MODE)
x = Bit is unknown
x = Bit is unknown
ADMSK1
R/W-0
R/W-1
MSK1
DS39775C-page 247
MSK0
R/W-0
R/W-1
SEN
bit 0
(2)
bit 0
(1)