PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 190

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
TABLE 11-3:
DS39775C-page 190
INTCON
PIR1
PIE1
IPR1
PMCONH
PMCONL
PMADDRH
PMDOUT1H
PMADDRL
PMDOUT1L
PMDOUT2H
PMDOUT2L
PMDIN1H
PMDIN1L
PMDIN2H
PMDIN2L
PMMODEH
PMMODEL
PMEH
PMEL
PMSTATH
PMSTATL
PADCFG1
Legend:
Note 1:
Name
2:
(2)
(1)
(1)
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and
addresses, but have different functions determined by the module’s operating mode.
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
(1)
(1)
/
/
GIE/GIEH
PTEN15
WAITB1
PMPEN
PTEN7
PMPIF
PMPIE
PMPIP
REGISTERS ASSOCIATED WITH PMP MODULE
BUSY
CSF1
Bit 7
OBE
CS2
IBF
—
PEIE/GIEL
PTEN14
WAITB0
IRQM1
PTEN6
OBUF
CSF0
ADIF
ADIE
ADIP
IBOV
Bit 6
CS1
—
—
Parallel Port Out Data, High Byte (Buffer 1)
Parallel Port Out Data, High Byte (Buffer 3)
Parallel Port Out Data, Low Byte (Buffer 0)
Parallel Port Out Data, Low Byte (Buffer 2)
WAITM3
Parallel Port In Data, High Byte (Buffer 1)
Parallel Port In Data, High Byte (Buffer 3)
PTEN13
TMR0IE
Parallel Port In Data, Low Byte (Buffer 0)
Parallel Port In Data, Low Byte (Buffer 2)
IRQM0
PTEN5
RC1IF
RC1IE
RC1IP
PSIDL
Parallel Master Port Address, Low Byte
Bit 5
ALP
—
—
—
ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN
WAITM2
PTEN12
PTEN4
INT0IE
INCM1
TX1IF
TX1IE
TX1IP
CS2P
Parallel Master Port Address, High Byte
Bit 4
—
—
—
WAITM1
PTEN11
SSP1IF
SSP1IE
SSP1IP
PTEN3
INCM0
CS1P
OB3E
RBIE
Bit 3
IB3F
—
MODE16 MODE1
WAITM0
PTEN10
TMR0IF
CCP1IF
CCP1IE
CCP1IP
PTEN2
OB2E
Bit 2
BEP
IB2F
—
TMR2IF
TMR2IE
TMR2IP
WAITE1
PTEN9
PTEN1
INT0IF
WRSP
© 2009 Microchip Technology Inc.
OB1E
Bit 1
IB1F
—
PMPTTL
TMR1IF
TMR1IE
TMR1IP
WAITE0
MODE0
PTEN8
PTEN0
RDSP
OB0E
RBIF
Bit 0
IB0F
on Page:
Values
Reset
61
64
64
64
66
67
66
66
66
66
66
66
66
66
67
67
67
67
67
67
67
67
62