PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 153

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

TABLE 10-12:
© 2009 Microchip Technology Inc.
RE0/AD8/
PMRD/P2D
RE1/AD9/
PMWR/P2C
RE2/AD10/
PMBE/P2B
RE3/AD11/
PMA13/P3C/
REFO
RE4/AD12/
PMA12/P3B
Legend:
Note 1:
Pin Name
2:
3:
4:
5:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PMP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when ECCP2MX Configuration bit is cleared (all devices in Microcontroller
mode).
Default configuration for PMP (PMPMX Configuration bit = 1).
Function
PMWR
PMRD
PMBE
AD10
AD11
AD12
PMA13
PMA12
AD8
AD9
P3C
REFO
P3B
PORTE FUNCTIONS
RE0
P2D
RE1
P2C
RE2
P2B
RE3
RE4
(3)
(3)
(1)
(1)
(3)
(3)
(3)
(5)
(5)
(5)
Setting
TRIS
0
1
x
x
x
x
0
0
1
x
x
x
x
0
0
1
x
x
x
0
0
1
x
x
x
0
x
0
1
x
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
TTL
DIG
DIG
DIG
DIG
DIG
TTL
DIG
DIG
I/O
ST
ST
ST
ST
ST
LATE<0> data output.
PORTE<0> data input.
External memory interface, address/data bit 8 output.
External memory interface, data bit 8 input.
Parallel Master Port read strobe pin.
Parallel Master Port read pin.
ECCP2 Enhanced PWM output, channel D; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<1> data output.
PORTE<1> data input.
External memory interface, address/data bit 9 output.
External memory interface, data bit 9 input.
Parallel Master Port write strobe pin.
Parallel Master Port write pin.
ECCP2 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<2> data output.
PORTE<2> data input.
External memory interface, address/data bit 10 output.
External memory interface, data bit 10 input.
Parallel Master Port byte enable.
ECCP2 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<3> data output.
PORTE<3> data input.
External memory interface, address/data bit 11 output.
External memory interface, data bit 11 input.
Parallel Master Port address.
ECCP3 Enhanced PWM output, channel C; takes priority over port
and PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Reference output clock.
LATE<4> data output.
PORTE<4> data input.
External memory interface, address/data bit 12 output.
External memory interface, data bit 12 input.
Parallel Master Port address.
ECCP3 Enhanced PWM output, channel B; takes priority over port and
PMP data. May be configured for tri-state during Enhanced PWM
shutdown events.
PIC18F87J50 FAMILY
Description
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DS39775C-page 153
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