PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 347

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

24.2
The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 24-1) keep CV
ence source rails. The voltage reference is derived
from the reference source; therefore, the CV
changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 28.0 “Electrical Characteristics”.
24.3
The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
CVROE bit is set. Enabling the voltage reference out-
put onto RA2 when it is configured as a digital input will
increase current consumption. Connecting RF5 as a
digital output with CVRSS enabled will also increase
current consumption.
FIGURE 24-2:
TABLE 24-1:
© 2009 Microchip Technology Inc.
CVRCON
CM1CON
CM2CON
TRISA
TRISF
ANCON0
ANCON1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.
Note 1:
Name
Note 1:
Voltage Reference Accuracy/Error
Connection Considerations
(1)
(1)
(1)
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
PCFG15
R is dependent upon the Comparator Voltage Reference Configuration bits, CVRCON<5> and CVRCON<3:0>.
CVREN
TRISA7
TRISF7
PCFG7
CON
CON
Bit 7
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
CV
Module
REF
COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
REF
PIC18F87J50
from approaching the refer-
PCFG14
CVROE
TRISA6
TRISF6
COE
COE
Bit 6
Impedance
Reference
—
Voltage
Output
R
(1)
PCFG13 PCFG12
TRISA5
TRISF5
CVRR
CPOL
CPOL
Bit 5
—
RF5
REF
output
EVPOL1
EVPOL1
CVRSS
TRISA4
TRISF4
PCFG4
Bit 4
EVPOL0
EVPOL0
PCFG11
TRISA3
TRISF3
PIC18F87J50 FAMILY
PCFG3
CVR3
Bit 3
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage
reference output for external connections to V
Figure 24-2 shows an example buffering technique.
24.4
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
24.5
A device Reset disables the voltage reference by
clearing bit, CVREN (CVRCON<7>). This Reset also
disconnects the reference from the RA2 pin by clearing
bit, CVROE (CVRCON<6>) and selects the high-voltage
range by clearing bit, CVRR (CVRCON<5>). The CVR
value select bits are also cleared.
Operation During Sleep
Effects of a Reset
+
–
PCFG10
TRISA2
TRISF2
PCFG2
CVR2
CREF
CREF
Bit 2
TRISA1
PCFG1
CCH1
CCH1
CVR1
Bit 1
CV
—
—
REF
Output
TRISA0
PCFG0
CVR0
CCH0
CCH0
Bit 0
DS39775C-page 347
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on Page:
Values
Reset
65
62
62
64
64
63
63
REF
.