PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 111

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

7.6.1
Figure 7-1 shows an example of 16-Bit Byte Write
mode for PIC18F87J10 family devices. This mode is
used for two separate 8-bit memories connected for
16-bit operation. This generally includes basic EPROM
and Flash devices. It allows table writes to byte-wide
external memories.
FIGURE 7-1:
© 2009 Microchip Technology Inc.
Note 1:
PIC18F87J50
2:
16-BIT BYTE WRITE MODE
A<19:16>
AD<15:8>
Upper order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
AD<7:0>
WRH
WRL
ALE
CE
OE
(1)
16-BIT BYTE WRITE MODE EXAMPLE
373
373
D<7:0>
A<19:0>
D<15:8>
PIC18F87J50 FAMILY
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.
A<x:0>
D<7:0>
CE
OE
(MSB)
WR
(2)
Address Bus
Data Bus
Control Lines
D<7:0>
DS39775C-page 111
OE
A<x:0>
D<7:0>
CE
(LSB)
WR
(2)