PIC18F86J50T-I/PT Microchip Technology, PIC18F86J50T-I/PT Datasheet - Page 474

• Manufacturer Part Number: PIC18F86J50T-I/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J50T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 65
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F86J50T-I/PTTR

PIC18F87J50 FAMILY
Timing Diagrams and Specifications
DS39775C-page 474
PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart En-
PWM Direction Change ........................................... 227
PWM Direction Change at Near 100% Duty Cycle .. 227
PWM Output ............................................................ 214
Read and Write, 8-Bit Data, Demultiplexed Address 183
Read, 16-Bit Data, Demultiplexed Address ............. 186
Read, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit
Read, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
Read, 8-Bit Data, Fully Multiplexed 16-Bit Address . 185
Read, 8-Bit Data, Partially Multiplexed Address ...... 183
Read, 8-Bit Data, Partially Multiplexed Address, Enable
Read, 8-Bit Data, Wait States Enabled, Partially Multi-
Repeated Start Condition ......................................... 268
Reset, Watchdog Timer (WDT), Oscillator Start-up Timer
Send Break Character Sequence ............................ 294
Slave Synchronization ............................................. 239
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 238
SPI Mode (Slave Mode, CKE = 0) ........................... 240
SPI Mode (Slave Mode, CKE = 1) ........................... 240
Synchronous Reception (Master Mode, SREN) ...... 297
Synchronous Transmission ...................................... 295
Synchronous Transmission (Through TXEN) .......... 296
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Not Tied to
Time-out Sequence on Power-up (MCLR Tied to V
Timer0 and Timer1 External Clock .......................... 443
Transition for Entry to Idle Mode ................................ 52
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Two-Speed Start-up (INTRC to HSPLL) ..
Transition for Wake From Idle to Run Mode .............. 52
Transition for Wake From Sleep (HSPLL) ................. 51
Transition From RC_RUN Mode to PRI_RUN Mode . 50
Transition From SEC_RUN Mode to PRI_RUN Mode
Transition to RC_RUN Mode ..................................... 50
USB Signal ............................................................... 458
Write, 16-Bit Data, Demultiplexed Address .............. 186
Write, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit
Write, 16-Bit Multiplexed Data, Partially Multiplexed Ad-
Write, 8-Bit Data, Fully Multiplexed 16-Bit Address . 185
Write, 8-Bit Data, Partially Multiplexed Address ...... 184
Write, 8-Bit Data, Partially Multiplexed Address, Enable
Write, 8-Bit Data, Wait States Enabled, Partially Multi-
AC Characteristics
Capture/Compare/PWM Requirements (Including ECCP
abled) ............................................................... 230
abled) ............................................................... 230
Address ............................................................ 187
dress ................................................................ 186
Strobe .............................................................. 184
plexed Address ................................................ 183
(OST) and Power-up Timer (PWRT) ................ 442
V
V
V
361
(HSPLL) ............................................................. 49
Address ............................................................ 187
dress ................................................................ 187
Strobe .............................................................. 185
plexed Address ................................................ 184
Internal RC Accuracy ....................................... 438
............................................................................ 59
DD
DD
DD
), Case 1 ...................................................... 58
), Case 2 ...................................................... 59
Rise < T
PWRT
) ............................................ 58
DD
, V
DD
Rise > T
PWRT
DD
)
,
TSTFSZ ........................................................................... 405
Two-Speed Start-up ................................................. 349, 361
Two-Word Instructions
TXSTAx Register
U
Universal Serial Bus
CLKO and I/O Requirements ................................... 439
EUSARTx Synchronous Receive Requirements ..... 455
EUSARTx Synchronous Transmission Requirements ...
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Master Mode, CKE =
Example SPI Mode Requirements (Slave Mode, CKE =
Example SPI Slave Mode Requirements (CKE = 1) 450
External Clock Requirements .................................. 437
I
I
MSSPx I
MSSPx I
Parallel Master Port Read Requirements ................ 445
Parallel Master Port Write Requirements ................ 446
PLL Clock ................................................................ 438
Program Memory Read Requirements .................... 440
Program Memory Write Requirements .................... 441
Reset, Watchdog Timer, Oscillator Start-up Timer, Pow-
Timer0 and Timer1 External Clock Requirements ... 443
USB Full-Speed Requirements ................................ 458
USB Low-Speed Requirements ............................... 458
Example Cases .......................................................... 77
BRGH Bit ................................................................. 283
Address Register (UADDR) ..................................... 318
Associated Registers ............................................... 334
Buffer Descriptor Table ............................................ 319
Buffer Descriptors .................................................... 319
Class Specifications and Drivers ............................. 336
Descriptors ............................................................... 336
Endpoint Control ...................................................... 317
Enumeration ............................................................ 336
External Pull-up Resistors ....................................... 315
Eye Pattern Test Enable .......................................... 315
Firmware and Drivers .............................................. 334
Frame Number Registers ........................................ 318
Frames .................................................................... 335
Internal Pull-up Resistors ......................................... 315
Internal Transceiver ................................................. 313
Interrupts ................................................................. 325
2
2
C Bus Data Requirements (Slave Mode) .............. 452
C Bus Start/Stop Bits Requirements (Slave Mode) .....
Modules) .......................................................... 444
455
0) ..................................................................... 447
1) ..................................................................... 448
0) ..................................................................... 449
451
er-up Timer and Brown-out Reset Requirements ..
442
Address Validation ........................................... 322
Assignment in Different Buffering Modes ........ 324
BDnSTAT Register (CPU Mode) ..................... 320
BDnSTAT Register (SIE Mode) ....................... 322
Byte Count ....................................................... 322
Example ........................................................... 319
Memory Map .................................................... 323
Ownership ....................................................... 319
Ping-Pong Buffering ........................................ 323
Register Summary ........................................... 324
Status and Configuration ................................. 319
and USB Transactions ..................................... 325
2
2
C Bus Data Requirements ....................... 454
C Bus Start/Stop Bits Requirements ........ 453
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