H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 950
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H8S-2350
Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.H8S-2350.pdf
(1025 pages)
- Current page: 950 of 1025
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Appendix B Internal I/O Register
TMDR0—Timer Mode Register 0
Rev. 3.00 Sep 15, 2006 page 916 of 988
REJ09B0330-0300
Bit
Initial value
Read/Write
:
:
:
—
—
7
1
—
—
6
1
TGRB Buffer Operation
BFB
R/W
0
1
5
0
TGRB operates normally
TGRB and TGRD used together
for buffer operation
BFA
R/W
TGRA Buffer Operation
4
0
0
1
TGRA operates normally
TGRA and TGRC used together
for buffer operation
H'FFD1
MD3
R/W
3
0
Legend: *: Don’t care
Notes: 1.
Mode
0
1
MD2
R/W
0
1
*
2
0
2.
MD3 is a reserved bit. In a write,
it should always be written with 0.
Phase counting mode cannot be
set for channels 0 and 3. In this
case, 0 should always be written
to MD2.
0
1
0
1
*
0
1
0
1
0
1
0
1
*
MD1
R/W
1
0
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
—
MD0
R/W
0
0
TPU0
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