H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 299

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Full Address Mode (Cycle Steal Mode)
Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address
mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to
external 16-bit, 2-state access space.
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Address bus
TEND
HWR
LWR
RD
Bus release
Figure 7.20 Example of Full Address Mode (Cycle Steal) Transfer
DMA
read
DMA
write
Bus release
DMA
read
DMA
write
Rev. 3.00 Sep 15, 2006 page 265 of 988
release
Bus
Section 7 DMA Controller (DMAC)
DMA
read
Last transfer
cycle
DMA
write
REJ09B0330-0300
DMA
dead
Bus
release